NCP5214A
http://onsemi.com
15
DETAILED OPERATING DESCRIPTION
General
The NCP5214A 2−in−1 Notebook DDR Power
Controller combines the efficiency of a PWM controller for
the VDDQ supply, with the simplicity of using a linear
regulator for the VTT termination voltage power supply.
The VDDQ output can be adjusted through the external
potential divider, while the VTT is internally set to track
half VDDQ.
The inclusion of VDDQ power good voltage monitor,
soft−start, VDDQ overcurrent protection, VDDQ
overvoltage and undervoltage protections, supply
undervoltage monitor, and thermal shutdown makes this
device a total power solution for high current DDR memory
system. The IC is packaged in DFN22.
Control Logic
The internal control logic is powered by VCCA. The IC
is enabled whenever VDDQEN is high (exceed 1.4 V). An
internal bandgap voltage, VREF, is then generated. Once
VREF reaches its regulation voltage, an internal signal
VREFGD will be asserted. This transition wakes up the
supply undervoltage monitor blocks, which will assert
VCCAGD if VCCA voltage is within certain preset levels.
The control logic accepts external signals at VCCA,
OCDDQ, VDDQEN, VTTEN, and FPWM pins to control
the operating state of the VDDQ and VTT regulators in
accordance with Table 1. A timing diagram is shown in
Figure 38.
VDDQ Switching Regulator in Normal Mode (S0)
The VDDQ regulator is a switching synchronous
rectification buck controller directly driving two external
N−Channel power FETs. An external resistor divider sets
the nominal output voltage. The control architecture is
voltage mode fixed frequency PWM with external
compensation and with switching frequency fixed at
400 kHz " 15%. As can be observed from Figure 1, the
VDDQ output voltage is divided down and fed back to the
inverting input of an internal error amplifier through
FBDDQ pin to close the loop at VDDQ = VFBDDQ ×
(1 + R1/R2). This amplifier compares the feedback voltage
with an internal VREF (= 0.800 V) to generate an error
signal for the PWM comparator. This error signal is further
compared with a fixed frequency RAMP waveform
derived from the internal oscillator to generate a
pulse−width−modulated signal. This PWM signal drives
the external N−Channel Power FETs via the TGDDQ and
BGDDQ pins. External inductor L and capacitor COUT1
filter the output waveform. The VDDQ output voltage
ramps up at a pre−defined soft−start rate when the IC enters
state S0 from S5. When in normal mode, and regulation of
VDDQ is detected, signal INREGDDQ will go HIGH to
notify the control logic block.
Input voltage feedforward is implemented to the RAMP
signal generation to reject the effect of wide input voltage
variation. With input voltage feedforward, the amplitude of
the RAMP is proportional to the input voltage.
For enhanced efficiency, an active synchronous switch is
used to eliminate the conduction loss contributed by the
forward voltage of a diode or Schottky diode rectifier.
Adaptive non−overlap timing control of the
complementary gate drive output signals is provided to
reduce large shoot−through current that degrades
efficiency.
Tolerance of VDDQ
The tolerance of VFBDDQ and the ratio of external
resistor divider R1/R2 both impact the precision of VDDQ.
With the control loop in regulation, VDDQ = VFBDDQ ×
(1 + R1/R2). With a worst case (for all valid operating
conditions) VFBDDQ tolerance of "1.5%, a worst case
range of "2.5% for VDDQ = 1.8 V will be assured if the
ratio R1/R2 is specified as 1.2500 "1%.
Table 1. State, Operation, Input and Output Condition Table
Mode
Input Conditions Operating Conditions Output Conditions
VCCA VOCDDQ VDDQEN VTTEN FPWM VDDQ VTTREF VTT TGDDQ BGDDQ PGOOD
S5 Low X X X X H−Z H−Z H−Z Low Low Low
S5 X Low X X X H−Z H−Z H−Z Low Low Low
S0 High High High High X Normal Normal Normal Normal Normal H−Z
S3 High High High Low High Standby Normal H−Z Standby
(Power−
saving)
Standby
(Power−
saving)
H−Z
S3 High High High Low Low Normal Normal H−Z Normal Normal H−Z
S5 X X Low X X H−Z H−Z H−Z Low Low Low
