IDT71124S12YI8

6.42
4
IDT71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
71124S12
(2)
71124S15 71124S20
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Read Cycle Time 12
____
15
____
20
____
ns
t
AA
Address Access Time
____
12
____
15
____
20 ns
t
ACS
Chip Select Access Time
____
12
____
15
____
20 ns
t
CLZ
(1)
Chip Select to Output in Low-Z 3
____
3
____
3
____
ns
t
CHZ
(1)
Chip Deselect to Output in High-Z 060708ns
t
OE
Output Enable to Output Valid
____
6
____
7
____
8ns
t
OLZ
(1)
Output Enable to Output in Low-Z 0
____
0
____
0
____
ns
t
OHZ
(1)
Output Disable to Output in High-Z 050507ns
t
OH
Output Hold from Address Change 4
____
4
____
4
____
ns
t
PU
(1)
Chip Select to Power-Up Time 0
____
0
____
0
____
ns
t
PD
(1)
Chip Deselect to Power-Down Time
____
12
____
15
____
20 ns
WRITE CYCLE
t
WC
Write Cycle Time 12
____
15
____
20
____
ns
t
AW
Address Valid to End of Write 8
____
12
____
15
____
ns
t
CW
Chip Select to End of Write 8
____
12
____
15
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WP
Write Pulse Width 8
____
12
____
15
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 6
____
8
____
9
____
ns
t
DH
Data Hold Time 0
____
0
____
0
____
ns
t
OW
(1)
Output active from End-of-Write 3
____
3
____
4
____
ns
t
WHZ
(1)
Write Enable to Output in High-Z 050508ns
3514 tbl 09
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
2. There is no industrial temperature offering for the 12ns speed grade.
6.42
IDT 71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges
5
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Read Cycle No. 1
(1)
Timing Waveform of Read Cycle No. 2
(1,2,4)
ADDRESS
3514 drw 05
OE
CS
DATA
OUT
(5)
(5)
(5)
(5)
DATA
OUT
VALID
HIGH IMPEDANCE
t
AA
t
RC
t
OE
t
ACS
t
OLZ
t
CHZ
t
CLZ
(3)
t
OHZ
V
CC
SUPPLY
CURRENT
t
PU
t
PD
I
CC
I
SB
.
DATA
OUT
ADDRESS
3514 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALIDPREVIOUS DATA
OUT
VALID
.
6.42
6
IDT71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
(1,2,4)
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
(1,4)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period.
5. Transition is measured ±200mV from steady state.
ADDRESS
CS
WE
DATA
OUT
DATAIN
3514 drw 07
(5)
(2)
(5)
(5)
DATAIN VALID
HIGH IMPEDANCE
t
WC
tAW
tAS
tWHZ
tWP
tCHZ
tOW
tDW
tDH
tWR
(3)(3)
.
CS
ADDRESS
DATA
IN
3514 drw 08
t
AW
t
WC
t
CW
t
AS
t
WR
t
DW
t
DH
DATA
IN
VALID
WE
.

IDT71124S12YI8

Mfr. #:
Manufacturer:
Description:
IC SRAM 1M PARALLEL 32SOJ
Lifecycle:
New from this manufacturer.
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