LTC3542
10
3542fa
Output Voltage Programming
The output voltage is set by a resistive divider according
to the following formula:
VV
R
R
OUT
=+
06 1
2
1
.
To improve the frequency response, a feed-forward capaci-
tor, C
F
, may also be used. Great care should be taken to
route the V
FB
line away from noise sources, such as the
inductor or the SW line.
Mode Selection and Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin that provides
mode selection and frequency synchronization. Connect-
ing this pin to GND enables Burst Mode operation, which
provides the best low current effi ciency at the cost of a
higher output voltage ripple. Connecting this pin to V
IN
selects pulse skip mode operation, which provides the
lowest output ripple at the cost of low current effi ciency.
The LTC3542 can also be synchronized to an external clock
signal with range from 1MHz to 3MHz by the MODE/SYNC
pin. During synchronization, the mode is set to pulse skip
and the top switch turn-on is synchronized to the falling
edge of the external clock.
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the effi ciency and which change would produce
the most improvement. Effi ciency can be expressed as:
Effi ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of
the losses in LTC3542 circuits: 1) V
IN
quiescent current,
2) I
2
R loss and 3) switching loss. V
IN
quiescent current
loss dominates the power loss at very low load currents,
whereas the other two dominate at medium to high load
currents. In a typical effi ciency plot, the effi ciency curve
at very low load currents can be misleading since the
actual power loss is of no consequence as illustrated in
Figure 2.
1) The V
IN
quiescent current is the DC supply current given
in the Electrical Characteristics which excludes MOSFET
charging current. V
IN
current results in a small (<0.1%)
loss that increases with V
IN
, even at no load.
2) I
2
R losses are calculated from the DC resistances of
the internal switches, R
SW
, and external inductor, R
L
. In
continuous mode, the average output current fl ows through
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
R
DS(ON)
and the duty cycle (D) as follows:
R
SW
= (R
DS(ON)TOP
)(D) + (R
DS(ON)BOT
)(1 – D)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses:
I
2
R losses = I
OUT
2
(R
SW
+ R
L
)
Figure 2. Power Loss vs Load Current
OUTPUT CURRENT (mA)
1
POWER LOSS (mW)
10
100
1000
0.1 10 100 1000
3542 F02
0.1
1
V
OUT
= 2.5V
V
OUT
= 1.8V
V
OUT
= 1.2V
V
IN
= 3.6V
Burst Mode OPERATION
APPLICATIONS INFORMATION
LTC3542
11
3542fa
3) The switching current is MOSFET gate charging current,
that results from switching the gate capacitance of the
power MOSFETs. Each time a MOSFET gate is switched
from low to high to low again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is a current out of
V
IN
that is typically much larger than the DC bias current.
In continuous mode, I
GATECHG
= f
O
(Q
T
+ Q
B
), where Q
T
and Q
B
are the gate charges of the internal top and bottom
MOSFET switches. The gate charge losses are proportional
to V
IN
and thus their effects will be more pronounced at
higher supply voltages.
Other “hidden” losses such as copper trace and internal
battery resistances can account for additional effi ciency
degradations in portable systems. The internal battery
and fuse resistance losses can be minimized by making
sure that C
IN
has adequate charge storage and very low
ESR at the switching frequency. Other losses include
diode conduction losses during dead-time and inductor
core losses generally account for less than 2% total ad-
ditional loss.
Thermal Considerations
In most applications the LTC3542 does not dissipate much
heat due to its high effi ciency. But in applications where the
LTC3542 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
the heat dissipated may exceed the maximum junction
temperature of the part. If the junction temperature reaches
approximately 60°C, both power switches will be turned
off and the SW node will become high impedance.
To avoid the LTC3542 from exceeding the maximum
junction temperature, the user need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and
θ
JA
is the thermal resistance from the junction of the die
to the ambient.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3542 in dropout at an
input voltage of 2.7V, a load current of 500mA and an
ambient temperature of 70°C. From the typical performance
graph of switch resistance, the R
DS(ON)
of the P-channel
switch at 70°C is approximately 0.7Ω. Therefore, power
dissipated by the part is:
P
D
= I
LOAD
2
• R
DS(ON)
= 175mW
For the DFN package, the θ
JA
is 102°C/W. Thus, the junc-
tion temperature of the regulator is:
T
J
= 70°C + 0.175 • 102 = 87.9°C
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction temperature
is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
• ESR, where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or dis-
charge C
OUT
, generating a feedback error signal used by the
regulator to return V
OUT
to its steady-state value. During
this recovery time, V
OUT
can be monitored for overshoot
or ringing that would indicate a stability problem.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a re-
view of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be caused
by switching loads with large (>1μF) bypass capacitors.
The discharged bypass capacitors are effectively put in
APPLICATIONS INFORMATION
LTC3542
12
3542fa
parallel with C
OUT
, causing a rapid drop in V
OUT
. No regula-
tor can deliver enough current to prevent this problem, if
the switch connecting the load has low resistance and is
driven quickly. The solution is to limit the turn-on speed of
the load switch driver. A Hot Swap
TM
controller is designed
specifi cally for this purpose and usually incorporates cur-
rent limit, short circuit protection and soft-start.
Design Example
As a design example, assume the LTC3542 is used in a single
lithium-ion battery-powered cellular phone application. The
V
IN
will be operating from a maximum of 4.2V down to
about 2.7V. The load current requirement is a maximum
of 0.5A, but most of the time it will be in standby mode,
requiring only 2mA. Effi ciency at both low and high load
currents is important. Output voltage is 1.8V.
With this information we can calculate L using:
L
fI
V
V
V
L
OUT
OUT
IN
=
1
1
••
Δ
Substituting V
OUT
= 1.8V, V
IN
= 4.2V, ΔI
L
= 200mA and
f = 2.25MHz gives:
L
V
MHz mA
V
V
μH=
=
18
2 25 200
1
18
42
228
.
.•
•–
.
.
.
Choosing a vendor’s closest inductor value of 2.2μH results
in a maximum ripple current of:
ΔI
V
MHz μH
V
V
L
=
=
18
225 22
1
18
42
207
.
.•.
•–
.
.
.88mA
Hot Swap is a trademark of Linear Technology Corporation.
C
IN
will require an RMS current rating of at least
0.25A I
LOAD(MAX)
/2 at temperature and C
OUT
will require
ESR of less than 0.2Ω. In most cases, ceramic capacitors
will satisfy these requirements. Select C
OUT
= 10μF and
C
IN
= 10μF.
For the feedback resistors, choose R1 = 75k, R2 can be
calculated from:
R
V
V
R
V
V
k
OUT
2
06
11
18
06
175=
=
.
–•
.
.
–• ==150k
Figure 3 shows the complete circuit along with its effi ciency
curve, load step response and recommended layout
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3542. These items are also illustrated graphically
in Figure 3b. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the V
IN
trace should be kept short, direct and
wide.
2. Does the V
FB
pin connect directly to the feedback re-
sistors? The resistive divider R1/R2 must be connected
between the (+) plate of C
OUT
and ground.
3. Does the (+) plate of C
IN
connect to V
IN
as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the (–) plates of C
IN
and C
OUT
as close as pos-
sible.
5. Keep the switching node, SW, away from the sensitive
V
FB
node.
APPLICATIONS INFORMATION

LTC3542EDC#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 500mA, 2.25MHz Sync Buck DC/DC Conv
Lifecycle:
New from this manufacturer.
Delivery:
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