MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
______________________________________________________________________________________ 13
Hiccup Fault Protection
The MAX15034 includes overload fault protection circuitry
that prevents damage to the power MOSFETs. The fault
protection consists of two digital fault integration blocks
that enable hiccuping under overcurrent conditions. This
circuit works as follows: for every clock cycle the current-
limit threshold is exceeded, the fault integration counter
increments by one count. Thus, if the current-limit condi-
tion persists, the counter reaches its shutdown threshold
in 32,768 counts and shuts down the external MOSFETs.
When the MAX15034 shuts down due to a fault, the
counter begins to count down (since the current-limit con-
dition has ended), once every 16 clock cycles. Thus, the
device counts down for 524,288 clock cycles. At this
point, switching resumes. This produces an effective duty
cycle of 6.25% power-up and 93.75% power-down under
fault conditions. With a switching frequency set to
250kHz, power-up and power-down times are approxi-
mately 131ms and 2.09s, respectively.
Control Loop
The MAX15034 uses an average current-mode control
topology to regulate the output voltage. The control
loop consists of an inner current loop and an outer volt-
age loop. The inner current loop controls the output
current, while the outer voltage loop controls the output
voltage. The inner current loop absorbs the inductor
pole, reducing the order of the outer voltage loop to
that of a single-pole system. Figure 2 is the block dia-
gram of OUT1’s control loop.
The current loop consists of a current-sense resistor,
R
SENSE
, a current-sense amplifier (CA1), a current-
error amplifier (CEA1), an oscillator providing the carri-
er ramp, and a PWM comparator (CPWM1). The
precision current-sense amplifier (CA1) amplifies the
sense voltage across R
SENSE
by a factor of 36. The
inverting input to CEA1 senses the output of CA1. The
output of CEA1 is the difference between the voltage-
error amplifier output (EAOUT1) and the gained-up volt-
age from CA1. The RC compensation network
connected to CLP1 provides external frequency com-
pensation for the respective CEA1 (see the
Compensation
section). The start of every clock cycle
enables the high-side driver and initiates a PWM on-
cycle. Comparator CPWM1 compares the output volt-
age from CEA1 against a 0 to 2V ramp from the
oscillator. The PWM on-cycle terminates when the ramp
voltage exceeds the error voltage from the current-error
amplifier (CEA1).
DRIVE
V
IN
V
OUT1
C
OUT
V
REF
= 0.61V
R
F
C
CFF
C
CF
I
L
R
CF
CSN1
CSP1
CLP1
2V
P-P
R
SENSE
LOAD
R1
R2
CA 1
CEA1
CPWM1
VEA1
Figure 2. Current and Voltage Loops
MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
14 ______________________________________________________________________________________
The outer voltage control loop consists of the voltage-
error amplifier (VEA1). The noninverting input (EAN1) is
externally connected to the midpoint of a resistive volt-
age-divider from OUT1 to EAN1 to AGND. The voltage
loop gain is set by using an external resistor from the
output of this amplifier (EAOUT1) to its inverting input
(EAN1). The noninverting input of (VEA1) is connected
to the 0.61V internal reference.
Current-Error Amplifier
The MAX15034 features two dedicated transconduc-
tance current-error amplifiers CEA1 and CEA2 with a
typical g
m
of 550µS and 320µA output sink and source
capability. The current-error amplifier outputs (CLP1 and
CLP2) serve as the inverting input to the PWM compara-
tors. CLP1 and CLP2 are externally accessible to pro-
vide frequency compensation for the inner current loops
(see C
CFF
, C
CF
, and R
CF
in Figure 2). Compensate the
current-error amplifier so that the inductor current down
slope, which becomes the up slope at the inverting
input of the PWM comparator, is less than the slope of
the internally generated voltage ramp (see the
Compensation
section).
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM1 or CPWM2) sets the
duty cycle for each cycle by comparing the current-
error amplifier output to a 2V
P-P
ramp. At the start of
each clock cycle an R-S flip-flop resets and the high-
side drivers (DH1 and DH2) turn on. The comparator
sets the flip-flop as soon as the ramp voltage exceeds
the current-error amplifier output voltage, thus terminat-
ing the on-cycle.
Voltage-Error Amplifier
The voltage-error amplifier (VEA_) sets the gain of the
voltage control loop. Its output clamps to 1.14V and
-0.234V relative to V
CM
= 0.61V. Set the MAX15034 out-
put voltage by connecting a voltage-divider from the
output to EAN_ to GND (see Figure 4). At no load, the
output of the voltage error amplifier is zero.
Use the equation below to calculate the no load voltage:
The voltage at full load is given by:
where V
OUT
is the voltage-positioning window
described in the
Adaptive Voltage Positioning
section.
Adaptive Voltage Positioning
Powering new-generation ICs requires new techniques
to reduce cost, size, and power dissipation. Voltage
positioning (Figure 5) reduces the total number of out-
put capacitors to meet a given transient response
requirement. Setting the no-load output voltage slightly
higher than the output voltage during nominally loaded
conditions allows a larger downward voltage excursion
when the output current suddenly increases.
Regulating at a lower output voltage under a heavy
load allows a larger upward-voltage excursion when
the output current suddenly decreases. A larger
allowed voltage-step excursion reduces the required
number of output capacitors and/or allows the use of
higher ESR capacitors.
The MAX15034 internal 0.6125V reference provides a
tolerance of ±1.25%. Using 0.1% resistors for R1 and
R2 allows a 4% variation from the nominal output volt-
age. This available voltage range allows the reduction
of the total number of output capacitors to meet a given
transient response requirement resulting in a voltage-
positioning window as shown in Figure 5.
From the allowable voltage-positioning window calcu-
late the value of R
F
from the equation below.
where V
OUT
is the allowable voltage-positioning win-
dow, R
SENSE
is the sense resistor, 36 is the current-
sense amplifier gain, and R
1
is as shown in Figure 4.
R
IR R
V
F
OUT SENSE
OUT
=
×××36
1
V
R
R
V
OUT FL OUT()
.+
0 6125 1
1
2
V
R
R
OUT NL()
.+
0 6125 1
1
2
MAX15034
MOSFET Gate Drivers (DH_, DL_)
The high-side drivers (DH1 and DH2) and low-side dri-
vers (DL1 and DL2) drive the gates of external n-channel
MOSFETs. The high-peak sink and source current capa-
bility of these drivers provides ample drive for the fast
rise and fall times of the switching MOSFETs. Faster rise
and fall times result in reduced switching losses. For low-
output, voltage-regulating applications where the duty
cycle is less than 50%, choose high-side MOSFETs (Q2
and Q4, Figure 6) with a moderate R
DS(ON)
and a very
low gate charge. Choose low-side MOSFETs (Q1 and
Q3, Figure 6) with very low R
DS(ON)
and moderate gate
charge. The driver block also includes a logic circuit that
provides an adaptive nonoverlap time (30ns typ) to pre-
vent shoot-through currents during transition. Figure 7
shows the dual-phase, single-output buck regulator.
2 x f
SW
(V/S)
RAMP
CLK
CSP_
CSN_
GM
IN
EN_
1.225V
CLP_
V
DD
BST_
DH_
LX_
DL_
PGND
A
V
= 36V/V
PWM
COMPARATOR
S
R
Q
Q
g
m
= 500µS
Figure 3. Current Comparator and MOSFET Driver Logic
LOAD
C
OUT
V
OUT
V
REF
= 0.61V
R
F
R
1
R
2
EAN_
EAOUT_
Figure 4. Voltage Error Amplifier
LOAD (A)
V
CNTR
NO LOAD
1/2 LOAD
FULL LOAD
VOLTAGE-POSITIONING WINDOW
V
CNTR
+ V
OUT
/2
V
CNTR
- V
OUT
/2
Figure 5. Defining the Voltage-Positioning Window
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
______________________________________________________________________________________ 15

MAX15034AAUI+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Controllers Configurable Synchronous Buck
Lifecycle:
New from this manufacturer.
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