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MAX15034AAUI+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
MAX15034
ripple current. A low-ESR input capacitor that can han-
dle the maximum input RMS ripple current of one chan-
nel must be used. The maximum RMS capacitor ripple
current is given by:
where I
MAX
is the full load current of the regulator. V
OUT
is the output voltage of the same regulator and C
IN
is C5
in Figure 6. The ESR of the input capacitors wastes
power from the input and heats up the capacitor.
Reducing the ESR is important to maintain a high overall
efficiency and in reducing the heating of the capacitors.
Output Capacitors
The worst-case peak-to-peak inductor ripple current,
the allowable peak-to-peak output ripple voltage, and
the maximum deviation of the output voltage during
step loads determine the capacitance and the ESR
requirements for the output capacitors. The output rip-
ple can be approximated as the inductor current ripple
multiplied by the output capacitor’s ESR (R
ESR_OUT
).
The peak-to-peak inductor current ripple is given by:
During a load step, the allowable deviation of the output
voltage during the fast transient load dictates the output
capacitance and ESR. The output capacitors supply the
load step until the controller responds with a greater duty
cycle. The response time (t
RESPONSE
) depends on the
closed-loop bandwidth of the regulator. The resistive
drop across the capacitor’s ESR and capacitor discharge
causes a voltage drop during a load step. Use a combi-
nation of SP polymer and ceramic capacitors for better
transient load and ripple/noise performance.
∆I
VD
Lf
L
OUT
SW
=
−
×
()1
II
VVV
V
CIN RMS MAX
OUT IN OUT
IN
()
()
≈
−
LOSS DESCRIPTION SEGMENT LOSS
Conduction Loss
Losses associated with MOSFET on-time and
on-resistance. I
RMS
is a function of load current
and duty cycle.
Gate Drive Loss
Losses associated with charging and
discharging the gate capacitance of the
MOSFET every cycle. Use the MOSFET’s (Q
G
)
specification.
Switching Loss
Losses during the drain voltage and drain
current transitions for every switching cycle.
Losses occur only during the Q
GS2
and Q
GD
time period and not during the initial Q
GS1
period. The initial Q
GS1
period is the rise in the
gate voltage from zero to V
TH.
R
DH_
is the high-
side MOSFET driver’s on-resistance and R
GATE
is the internal gate resistance of the high-side
MOSFET (Q
GD
and Q
GS2
are found in the
MOSFET data sheet).
Output Loss
Losses associated with Q
OSS
of the MOSFET
occur every cycle when the high-side MOSFET
turns on. The losses are caused by both
MOSFETs, but are dissipated in the high-side
MOSFET.
Table 1. High-Side MOSFET Losses
PIR
where I
V
V
CONDUCTION RMS DS ON
RMS
OUT
IN
=×
≈×
2
()
II
LOAD
PVQQf
GATEDRIVE DD G GD SW
=×
()
×−
PVI
SWITCH IN LOA
=×
DDSW
GS GD
GATE
f
QQ
I
××
+()
2
GATE
DD
DH
where I
V
R
=
× (
_
2 ++ R
GATE
)
=
+
××P
QQ
Vf
OUTPUT
OSS HS OSS LS
IN SW
() ()
2
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
______________________________________________________________________________________ 19
MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
20 ______________________________________________________________________________________
Keep the maximum output-voltage deviation less than
or equal to the adaptive voltage-positioning window
(∆V
OUT
). During a load step, assume a 50% contribu-
tion each from the output capacitance discharge and
the voltage drop across the ESR (∆V
OUT
= ∆V
ESR_OUT
+ ∆V
Q_OUT
). Use the following equations to calculate
the required ESR and capacitance value:
where I
LOAD_STEP
is the step in load current and
t
RESPONSE
is the response time of the controller.
Controller response time depends on the control-loop
bandwidth. C
OUT
is C6 and C7 in Figure 6.
Current Limit
The MAX15034 incorporates two forward current-limit
protection mechanisms, average current limit and hic-
cup fault current limit, which accurately limit the output
current per phase. The average current-mode control
technique of the MAX15034 accurately limits the maxi-
mum average output current per phase. The
MAX15034 senses the voltage across either a sense
resistor or can implement lossless inductor sense,
sensing the voltage across the parasitic resistance of
the inductor (DCR). Use either mechanism to limit the
maximum inductor current.
The minimum average voltage, at which the voltage
across the current-sense resistor is clamped, is either
internally set to 20.4mV or is controlled by the voltage
at AVGLIMIT. The AVGLIMIT ground threshold of
550mV (typ) is the threshold above which the control of
the average current-limit voltage is transferred from the
internal 20.4mV (min) reference to the externally set
V
AVGLIMIT
. For using the internal average current-limit
value, short AVGLIMIT to AGND. The minimum (inter-
nally set) average current limit is set at:
For example, the current-sense resistor:
for a maximum output current limit of 10A. A standard
value is 2mΩ. Also, adjust the value of the current-
sense resistor to compensate for parasitics associated
with the PCB. Select a noninductive resistor with an
appropriate wattage rating.
The implementation is shown in Figure 8.
When sensing directly across the inductor, connect an
RC circuit directly across the shunt or inductor (see
Figure 9).
R
mV
A
m
SENSE
==
20 4
10
204
.
. Ω
I
mV
R
LIMIT MIN
SENSE
()
.
=
20 4
R
V
I
C
It
V
ESR OUT
ESR OUT
LOAD STEP
OUT
LOAD STEP RESPONSE
Q OUT
_
_
_
_
_
=
=
×
∆
∆
LOSS DESCRIPTION SEGMENT LOSSES
Conduction Loss
Losses associated with MOSFET on-time, I
RMS
is a function of load current and duty cycle.
Gate Drive Loss
Losses associated with charging and
discharging the gate of the MOSFET every
cycle. There is no Q
GD
charging involved in this
MOSFET due to the zero-voltage turn-on. The
charge involved is (Q
G
- Q
GD
).
Table 2. Low-Side MOSFET Losses
PIR
where I
VV
V
I
CONDUCTION RMS DS ON
RMS
IN OUT
IN
LOAD
=×
≈
−
×
2
()
PVQQf
GATEDRIVE DD G GD SW
=×
()
×−
Note: The gate drive losses are distributed between the drivers and the MOSFETs in the ratio of the gate driver’s resistance and the
MOSFET’s internal gate resistance.
MAX15034
Set the RC time constant to be 1.1 to 1.2 times the
inductor time constant (L/DCR). Select C1 to be in the
0.1µF to 0.47µF range, and then calculate R1 from:
In some applications, it may be useful to add a resistor
(R2 in Figure 9) in series with the CSN_ connection to
minimize input offset error. Set R2 equal to R1. It may
also prove useful to add capacitor C3 (Figure 9) in
parallel with R2 to aid in short-circuit recovery. Set C3
equal to C1. Finally, it may be helpful to add a 100pF
(C2) capacitor immediately across the CSP_ and CSN_
inputs to minimize high-frequency noise pick-up at the
IC in some applications.
For current-sense resistors that have a noticeable
inductance component, use lossless inductor sense
implementation (and design procedure). See Figure 10.
Table 3 highlights the tradeoffs of each current-sense
method.
Rk
LH
DCR m C F
1
12
1
[]
.[]
[] []
Ω
Ω
=
×
×
µ
µ
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
______________________________________________________________________________________ 21
L
OUT
R
SENSE
V
OUT
LX_
CSP_
MAX15034
CSN_
Figure 8. Noninductive Resistive Sense
L
INDUCTOR
DCR
V
OUT
LX_
CSP_
MAX15034
CSN_
C2*
R1
C1
C3*
*OPTIONAL.
R2*
Figure 9. Lossless Inductor Sense
Table 3. Current-Sense Configurations
METHOD
CURRENT-SENSE
ACCURACY
INDUCTOR-SATURATION
PROTECTION
CURRENT-SENSE POWER
LOSS (EFFICIENCY)
Output Current-Sense Resistor High Allowed (highest accuracy) R
SENSE
x I
OUT
2
Equivalent Inductor DC Resistance Low Allowed No additional loss
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MAX15034AAUI+T

Mfr. #:
Buy MAX15034AAUI+T
Manufacturer:
Maxim Integrated
Description:
Switching Controllers Configurable Synchronous Buck
Lifecycle:
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