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SCAN182245A
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register Definition Index
Bit No. Pin Name Pin No. Pin Type Scan Cell Type Bit No. Pin Name Pin No. Pin Type Scan Cell Type
79 DIR1 3 Input TYPE1
Control
Signals
35 B1
0
2 Input TYPE1
B1in
78 G1
54 Input TYPE1 34 B1
1
4 Input TYPE1
77 AOE
1
Internal TYPE2 33 B1
2
5 Input TYPE1
76 BOE
1
Internal TYPE2 32 B1
3
7 Input TYPE1
75 DIR2 26 Input TYPE1 31 B1
4
8 Input TYPE1
74 G2
31 Input TYPE1 30 B1
5
10 Input TYPE1
73 AOE
2
Internal TYPE2 29 B1
6
11 Input TYPE1
72 BOE
2
Internal TYPE2 28 B1
7
13 Input TYPE1
71 A1
0
55 Input TYPE1
A1in
27 B1
8
14 Input TYPE1
70 A1
1
53 Input TYPE1 26 B2
0
15 Input TYPE1
B2in
69 A1
2
52 Input TYPE1 25 B2
1
16 Input TYPE1
68 A1
3
50 Input TYPE1 24 B2
2
18 Input TYPE1
67 A1
4
49 Input TYPE1 23 B2
3
19 Input TYPE1
66 A1
5
47 Input TYPE1 22 B2
4
21 Input TYPE1
65 A1
6
46 Input TYPE1 21 B2
5
22 Input TYPE1
64 A1
7
44 Input TYPE1 20 B2
6
24 Input TYPE1
63 A1
8
43 Input TYPE1 19 B2
7
25 Input TYPE1
62 A2
0
42 Input TYPE1
A2in
18 B2
8
27 Input TYPE1
61 A2
1
41 Input TYPE1 17 A1
0
55 Output TYPE2
A1out
60 A2
2
39 Input TYPE1 16 A1
1
53 Output TYPE2
59 A2
3
38 Input TYPE1 15 A1
2
52 Output TYPE2
58 A2
4
36 Input TYPE1 14 A1
3
50 Output TYPE2
57 A2
5
35 Input TYPE1 13 A1
4
49 Output TYPE2
56 A2
6
33 Input TYPE1 12 A1
5
47 Output TYPE2
55 A2
7
32 Input TYPE1 11 A1
6
46 Output TYPE2
54 A2
8
30 Input TYPE1 10 A1
7
44 Output TYPE2
53 B1
0
2 Output TYPE2
B1out
9A1
8
43 Output TYPE2
52 B1
1
4 Output TYPE2 8 A2
0
42 Output TYPE2
A2out
51 B1
2
5 Output TYPE2 7 A2
1
41 Output TYPE2
50 B1
3
7 Output TYPE2 6 A2
2
39 Output TYPE2
49 B1
4
8 Output TYPE2 5 A2
3
38 Output TYPE2
48 B1
5
10 Output TYPE2 4 A2
4
36 Output TYPE2
47 B1
6
11 Output TYPE2 3 A2
5
35 Output TYPE2
46 B1
7
13 Output TYPE2 2 A2
6
33 Output TYPE2
45 B1
8
14 Output TYPE2 1 A2
7
32 Output TYPE2
44 B2
0
15 Output TYPE2
B2out
0A2
8
30 Output TYPE2
43 B2
1
16 Output TYPE2
42 B2
2
18 Output TYPE2
41 B2
3
19 Output TYPE2
40 B2
4
21 Output TYPE2
39 B2
5
22 Output TYPE2
38 B2
6
24 Output TYPE2
37 B2
7
25 Output TYPE2
36 B2
8
27 Output TYPE2
www.fairchildsemi.com 8
SCAN182245A
SCAN ABT Live Insertion and Power Cycling Characteristics
SCAN ABT is intended to serve in Live Insertion backplane
applications. It provides 2nd Level Isolation
1
which indi-
cates that while external circuitry to control the output
enable pin is unnecessary, there may be a need to imple-
ment differential length backplane connector pins for V
CC
and GND. As well, pre-bias circuitry for backplane pins
may be necessary to avoid capacitive loading effects dur-
ing live insertion.
SCAN ABT provides control of output enable pins during
power cycling via the circuit in Figure 1. It essentially con-
trols the G
n
pin until V
CC
reaches a known level.
During power-up, when V
CC
ramps through the 0.0V to
0.7V range, all internal device circuitry is inactive, leaving
output and I/O pins of the device in high impedance. From
approximately 0.8V to 1.8V V
CC
, the Power-On-Reset cir-
cuitry, (POR), in Figure 1 becomes active and maintains
device high impedance mode. The POR does this by pro-
viding a low from its output that resets the flip-flop The out-
put, Q
, of the flip-flop then goes high and disables the NOR
gate from an incidental low input on the G
n
pin. After 1.8V
V
CC
, the POR circuitry becomes inactive and ceases to
control the flip-flop. To bring the device out of high imped-
ance, the G
n
input must receive an inactive-to-active transi-
tion, a high-to-low transition on G
n
in this case to change
the state of the flip-flop. With a low on the Q
output of the
flip-flop, the NOR gate is free to allow propagation of a G
n
signal.
During power-down, the Power-On-Reset circuitry will
become active and reset the flip-flop at approximately 1.8V
V
CC
. Again, the Q output of the flip-flop returns to a high
and disables the NOR gate from inputs from the G
n
pin.
The device will then remain in high impedance for the
remaining ramp down from 1.8V to 0.0V V
CC
.
Some suggestions to help the designer with live insertion
issues:
The G
n
pin can float during power-up until the Power-
On-Reset circuitry becomes inactive.
The G
n
pin can float on power-down only after the
Power-On-Reset has become active.
The description of the functionality of the Power-On-Reset
circuitry can best be described in the diagram of Figure 2.
FIGURE 1.
1
Section 7, Design Consideration for Fault Tolerant Backplanes, Application Note AN-881.
SCAN ABT includes additional power-on reset circuitry not otherwise included in ABT devices.
FIGURE 2.
9 www.fairchildsemi.com
SCAN182245A
Absolute Maximum Ratings(Note 2) Recommended Operating
Conditions
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 4: Guaranteed not tested.
Storage Temperature 65°C to +150°C
Ambient Temperature under Bias
55°C to +125°C
Junction Temperature under Bias
55°C to +150°C
V
CC
Pin Potential to Ground Pin 0.5V to +7.0V
Input Voltage (Note 3)
0.5V to +7.0V
Input Current (Note 3)
30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
0.5V to +5.5V
in the HIGH State
0.5V to V
CC
Current Applied to Output
in LOW State (Max) Twice the Rated I
OL
(mA)
DC Latchup Source Current
500 mA
Over Voltage Latchup (I/O) 10V
ESD (HBM) Min. 2000V
Free Air Ambient Temperature
40°C to +85°C
Supply Voltage
+4.5V to +5.5V
Minimum Input Edge Rate (
V/t)
Data Input 50 mV/ns
Enable Input 20 mV/ns
Symbol Parameter
V
CC
Min Typ Max Units Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized LOW Signal
V
CD
Input Clamp Diode Voltage Min 1.2 V I
IN
= 18 mA
V
OH
Output HIGH Voltage Min 2.5 V I
OH
= 3 mA
Min 2.0 V I
OH
= 32 mA
V
OL
Output LOW Voltage Min 0.8 V I
OL
= 15 mA
I
IH
Input HIGH Current
All Others
Max 5 µAV
IN
= 2.7V (Note 4)
Max 5 µAV
IN
= V
CC
TMS, TDI Max 5 µAV
IN
= V
CC
I
BVI
Input HIGH Current Breakdown Test Max 7 µAV
IN
= 7.0V
I
BVIT
Input HIGH Current Breakdown Test (I/O) Max 100 µAV
IN
= 5.5V
I
IL
Input LOW Current
All Others
Max 5 µAV
IN
= 0.5V (Note 4)
Max 5 µAV
IN
= 0.0V
TMS, TDI Max 385 µAV
IN
= 0.0V
V
ID
Input Leakage Test 0.0 4.75 V I
ID
= 1.9 µA
All Other Pins Grounded
I
IH
+ I
OZH
Output Leakage Current Max 50 µAV
OUT
= 2.7V
I
IL
+ I
OZL
Output Leakage Current Max 50 µAV
OUT
= 0.5V
I
OZH
Output Leakage Current Max 50 µAV
OUT
= 2.7V
I
OZL
Output Leakage Current Max 50 µAV
OUT
= 0.5V
I
OS
Output Short-Circuit Current Max 100 275 mA V
OUT
= 0.0V
I
CEX
Output HIGH Leakage Current Max 50 µAV
OUT
= V
CC
I
ZZ
Bus Drainage Test 0.0 100 µAV
OUT
= 5.5V, All Others GND
I
CCH
Power Supply Current Max 250 µAV
OUT
= V
CC
; TDI, TMS = V
CC
Max 1.0 mA V
OUT
= V
CC
; TDI, TMS = GND
I
CCL
Power Supply Current Max mA V
OUT
= LOW; TDI, TMS = V
CC
Max 65.8 mA V
OUT
= LOW; TDI, TMS = GND
I
CCZ
Power Supply Current Max 250 µA TDI, TMS = V
CC
Max 1.0 mA TDI, TMS = GND
I
CCT
Additional I
CC
/Input
All Other Inputs Max 2.9 mA V
IN
= V
CC
2.1V
TDI, TMS inputs Max 3 mA V
IN
= V
CC
2.1V
I
CCD
Dynamic I
CC
No Load Max 0.2 mA/ Outputs Open
MHz One Bit Toggling, 50% Duty Cycle

SCAN182245ASSC

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Bus Transceivers Non-Inverting Trans
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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