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NCP1571DG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
Semiconductor Components Industries, LLC, 2004
October, 2004 − Rev. 4
1 Publication Order Number
NCP1571/D
NCP1571
Low Voltage Synchronous
Buck Controller
The NCP1571 is a low voltage buck controller. It provides the
control for a DC−DC power solution producing an output voltage as
low as 0.980 V over a wide current range. The NCP1571−based
solution is powered from 12 V with the output derived from a 2−7 V
supply. It contains all required circuitry for a synchronous NFET buck
regulator using the V
2
control method to achieve the fastest possible
transient response and best overall regulation. NCP1571 operates at a
fixed internal 200 kHz frequency and is packaged in an SOIC−8.
This device provides undervoltage lockout protection, Soft−Start,
Power Good with delay, and built−in adaptive non−overlap. During
undervoltage lockout, the NCP1571 controller allows the power
supply output to drift down, allowing the load time to shut off. This
operation distinguishes the NCP1571 from other parts in its family.
Features
• Pb−Free Package is Available
• 0.980 V ± 1.0% Reference Voltage
• V
2
Control Topology
• 200 ns Transient Response
• Programmable Soft−Start
• Power Good
• Programmable Power Good Delay
• 40 ns Gate Rise and Fall Times (3.3 nF Load)
• Adaptive FET Non−Overlap Time
• Fixed 200 kHz Oscillator Frequency
• Undervoltage Lockout Holds Both Gate Outputs Low
• On/Off Control Through Use of the COMP Pin
• Overvoltage Protection through Synchronous MOSFETs
• Synchronous N−Channel Buck Design
• Dual Supply, 12 V Control, 2−7 V Power Source
SOIC−8
D SUFFIX
CASE 751
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
GATE(H)COMP
18
GATE(L)PGDELAY
V
FB
PWRGD
GNDV
CC
PIN CONNECTIONS
1
8
1571
ALYW
1
8
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†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Device Package Shipping
†
ORDERING INFORMATION
NCP1571D SOIC−8 98 Units/Rail
NCP1571DR2 SOIC−8
2500 Tape & Reel
NCP1571DR2G SOIC−8
(Pb−Free)
2500 Tape & Reel
MARKING
DIAGRAM
NCP1571
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2
Figure 1. Applications Circuit
GND
V
FB
GATE(L)
GATE(H)
V
CC
PWRGD
PGDELAY
COMP
NCP1571
C13
0.1 F
C12
0.01 F
R1
50 k
12 V V
LOGIC
5.0 V
NTD4302
NTD4302
2.7 H
3.3 k
+
+
33 F/8.0 V/1.6 Arms
56 F/4.0 V/1.6 Arms
SP−CAP 40 m
GND
Q1
Q2
+
+
C3C2C1
+ + +
GND
2.5 V/10 A
C8 C9 C10 C11
5.1 k
R3
R5
L1
100 pF
C6
C4
0.47 F
PWRGD
10
R4
MAXIMUM RATINGS
Rating Value Unit
Operating Junction Temperature 150 °C
Storage Temperature Range −65 to 150 °C
ESD Susceptibility (Human Body Model) 2.0 kV
Lead Temperature Soldering: Reflow: (Note 1) 230 peak °C
Moisture Sensitivity Level 2 −
Package Thermal Resistance, SOIC−8
Junction−to−Case, R
JC
Junction−to−Ambient, R
JA
48
165
°C/W
°C/W
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 60 second maximum above 183°C.
MAXIMUM RATINGS
Pin Name Pin Symbol V
MAX
V
MIN
I
SOURCE
I
SINK
IC Power Input V
CC
15 V −0.5 V N/A 1.5 A Peak
450 mA DC
Compensation Capacitor COMP 6.0 V −0.5 V 10 mA 10 mA
Voltage Feedback Input V
FB
6.0 V −0.5 V 1.0 mA 1.0 mA
Power Good Output PWRGD 15 V −0.5 V 1.0 mA 20 mA
Power Good Delay PGDELAY 6.0 V −0.5 V 1.0 mA 10 mA
High−Side FET Driver GATE(H) 15 V −0.5 V
−2.0 V for 50 ns
1.5 A Peak
200 mA DC
1.5 A Peak
200 mA DC
Low−Side FET Driver GATE(L) 15 V −0.5 V
−2.0 V for 50 ns
1.5 A Peak
200 mA DC
1.5 A Peak
200 mA DC
Ground GND 0.5 V −0.5 V 1.5 A Peak
450 mA DC
N/A
NCP1571
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3
ELECTRICAL CHARACTERISTICS (0°C < T
J
< 125°C, 11.4 V < V
CC
< 12.6 V, C
GATE(H)
= C
GATE(L)
= 3.3 nF,
C
PGDELAY
= 0.01 F, C
COMP
= 0.1 F; unless otherwise specified.)
Characteristic
Test Conditions Min Typ Max Unit
Error Amplifier
V
FB
Bias Current V
FB
= 0 V − 0.2 2.0 A
COMP Source Current COMP = 1.5 V, V
FB
= 0.8 V 15 30 60 A
COMP Sink Current COMP = 1.5 V, V
FB
= 1.2 V 15 30 60 A
Reference Voltage COMP = V
FB
T
J
< 25°C
0.970
0.965
0.980
0.980
0.990
0.995
V
V
COMP Max Voltage V
FB
= 0.8 V 2.4 2.7 − V
COMP Min Voltage V
FB
= 1.2 V − 0.1 0.2 V
COMP Fault Discharge Current at UVLO COMP = 1.2 V, V
CC
= 6.9 V 0.5 1.7 − mA
COMP Fault Discharge Threshold to
Reset UVLO
− 0.1 0.25 0.3 V
Open Loop Gain − − 98 − dB
Unity Gain Bandwidth − − 20 − kHz
PSRR @ 1.0 kHz − − 70 − dB
Output Transconductance − − 32 − mmho
Output Impedance − − 2.5 − M
GATE(H) and GATE(L)
Rise Time 1.0 V < GATE(L), GATE(H) < V
CC
− 2.0 V − 40 80 ns
Fall Time V
CC
− 2.0 V < GATE(L), GATE(H) < 1.0 V − 40 80 ns
GATE(H) to GATE(L) Delay GATE(H) < 2.0 V, GATE(L) > 2.0 V 40 60 100 ns
GATE(L) to GATE(H) Delay GATE(L) < 2.0 V, GATE(H) > 2.0 V 40 60 100 ns
Minimum Pulse Width GATE(X) = 4.0 V − 250 − ns
High Voltage (AC) Measure GATE(L) or GATE(H)
0.5 nF < C
GATE(H)
= C
GATE(L)
< 10 nF
Note 2
V
CC
− 0.5 V
CC
− V
Low Voltage (AC) Measure GATE(L) or GATE(H)
0.5 nF < C
GATE(H)
= C
GATE(L)
< 10 nF
Note 2
− 0 0.5 V
GATE(H)/(L) Pulldown Resistance to GND. Note 2 20 50 115 k
Power Good
Lower Threshold, V
O
Rising
T
J
< 25°C
0.852
0.847
0.882
0.882
0.912
0.917
V
V
Lower Threshold, V
O
Falling
T
J
< 25°C
0.663
0.658
0.685
0.685
0.709
0.714
V
V
PWRGD Low Voltage I
SINK
= 1.0 mA, V
FB
= 0 V − 0.15 0.4 V
Delay Charge Current PGDELAY = 2.0 V 7.0 12 18 A
Delay Clamp Voltage − 3.45 4.0 4.3 V
Delay Charge Threshold Ramp PGDELAY, Monitor PWRGD 3.1 3.3 3.5 V
Delay Discharge Current at UVLO PGDELAY = 0.5 V, V
CC
= 6.9 V 0.5 2.0 − mA
2. Guaranteed by design. Not tested in production.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

NCP1571DG

Mfr. #:
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Manufacturer:
ON Semiconductor
Description:
Switching Controllers Low Voltage Synchronous Buck
Lifecycle:
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