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NCP1571DG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
NCP1571
http://onsemi.com
10
Figure 22. Idealized Waveforms
8.5 V
0.5 V
V
IN
V
COMP
V
FB
GATE(H)
UVLO STARTUP NORMAL OPERATION
t
S
Normal Operation
During normal operation, the duty cycle of the gate drivers
remains approximately constant as the V
2
control loop
maintains the regulated output voltage under steady state
conditions. Variations in supply line or output load conditions
will result in changes in duty cycle to maintain regulation.
Input Supplies
The NCP1571 can be used in applications where a 12 V
supply is available along with a lower voltage supply. Often
the lower voltage supply is 5 V, but it can be any voltage less
than the 12 V supply minus the required gate drive voltage
of the top MOSFET. The greater the difference between the
two voltages, the better the efficiency due to increasing V
GS
available to turn on the upper MOSFET. In order to maintain
power supply stability, the lower supply voltage should be
at least 1.5 times the desired voltage.
A lower supply voltage between 2−7 V is recommended.
Gate Charge Effect on Switching Times
When using the onboard gate drivers, the gate charge has
an important effect on the switching times of the FETs. A
finite amount of time is required to charge the effective
capacitor seen at the gate of the FET. Therefore, the rise and
fall times rise linearly with increased capacitive loading.
Transient Response
The 200 ns reaction time of the control loop provides fast
transient response to any variations in input voltage and
output current. Pulse−by−pulse adjustment of duty cycle is
provided to quickly ramp the inductor current to the required
level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
capacitors during the time required to slew the inductor
current. For better transient response, several high
frequency and bulk output capacitors are usually used.
Overvoltage Protection
Overvoltage protection is provided as a result of the
normal operation of the V
2
control method and requires no
additional external components. The control loop responds
to an overvoltage condition within 200 ns, turning off the
upper MOSFET and disconnecting the regulator from its
input voltage. This results in a crowbar action to clamp the
output voltage, preventing damage to the load. The regulator
remains in this state until the overvoltage condition ceases.
Power Good
The PWRGD pin is asserted when the output voltage is
within regulation limits. Sensing for the PWRGD pin is
achieved through the V
FB
pin. When the output voltage is
rising, PWRGD goes high at 90% of the designed output
voltage. When the output voltage is falling, PWRGD goes
low at 70% of the designed output voltage. PWRGD is an
open−collector output and should be externally pulled to
logic high through a resistor to limit current to no more than
20 mA. Figure 23 shows the hysteretic nature of the
PWRGD pin’s operation.
Figure 23. PWRGD Assertion
High
Low
V
OUT
70% 90%
Percent of
Designed V
OUT
PWRGD
Shutdown
When the input voltage connected to V
CC
falls through the
lower threshold of the UVLO comparator, a fault latch is set.
The fault latch provides a signal that forces both GATE(H)
and GATE(L) into their logic low state, producing a
high−impedance output at the converter switch node. At the
same time, the latch also turns on two transistors which pull
down on the COMP and PGDELAY pins, quickly
discharging their external capacitors, and allowing PWRGD
to fall.
CONVERTER DESIGN
Selection of the Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are their ESR
Equivalent Series Resistance (ESR), and Equivalent Series
Inductance (ESL). For best transient response, a
combination of low value/high frequency and bulk
capacitors placed close to the load will be required.
In order to determine the number of output capacitors the
maximum voltage transient allowed during load transitions
has to be specified. The output capacitors must hold the
output voltage within these limits since the inductor current
NCP1571
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11
can not change with the required slew rate. The output
capacitors must therefore have a very low ESL and ESR.
The voltage change during the load current transient is:
V
OUT
I
OUT
ESL
t
ESR
t
TR
C
OUT
where:
I
OUT
/ t = load current slew rate;
I
OUT
= load transient;
t = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors
and circuit traces;
t
TR
= output voltage transient response time.
The designer has to independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
depending on the load current transition) results from the
total output capacitor ESR.
The maximum allowable ESR can then be determined
according to the formula:
ESR
MAX
V
ESR
I
OUT
where:
V
ESR
= change in output voltage due to ESR (assigned
by the designer)
Once the maximum allowable ESR is determined, the
number of output capacitors can be found by using the
formula:
Number of capacitors
ESR
CAP
ESR
MAX
where:
ESR
CAP
= maximum ESR per capacitor (specified in
manufacturer’s data sheet).
ESR
MAX
= maximum allowable ESR.
The actual output voltage deviation due to ESR can then
be verified and compared to the value assigned by the
designer:
V
ESR
I
OUT
ESR
MAX
Similarly, the maximum allowable ESL is calculated from
the following formula:
ESL
MAX
V
ESL
t
I
Selection of the Input Inductor
A common requirement is that the buck controller must
not disturb the input voltage. One method of achieving this
is by using an input inductor and a bypass capacitor. The
input inductor isolates the supply from the noise generated
in the switching portion of the buck regulator and also limits
the inrush current into the input capacitors upon power up.
The inductor’s limiting effect on the input current slew rate
becomes increasingly beneficial during load transients. The
worst case is when the load changes from no load to full load
(load step), a condition under which the highest voltage
change across the input capacitors is also seen by the input
inductor. The inductor successfully blocks the ripple current
while placing the transient current requirements on the input
bypass capacitor bank, which has to initially support the
sudden load change.
The minimum inductance value for the input inductor is
therefore:
L
IN
V
(dIdt)
MAX
where:
L
IN
= input inductor value;
V = voltage seen by the input inductor during a full load
swing;
(dI/dt)
MAX
= maximum allowable input current slew rate.
The designer must select the LC filter pole frequency so
that at least 40 dB attenuation is obtained at the regulator
switching frequency. The LC filter is a double−pole network
with a slope of −2.0, a roll−off rate of −40 dB/dec, and a
corner frequency:
f
C
1
2 LC
where:
L = input inductor;
C = input capacitor(s).
Selection of the Output Inductor
There are many factors to consider when choosing the
output inductor. Maximum load current, core and winding
losses, ripple current, short circuit current, saturation
characteristics, component height and cost are all variables
that the designer should consider. However, the most
important consideration may be the effect inductor value has
on transient response.
The amount of overshoot or undershoot exhibited during
a current transient is defined as the product of the current
step and the output filter capacitor ESR. Choosing the
inductor value appropriately can minimize the amount of
energy that must be transferred from the inductor to the
capacitor or vice−versa. In the subsequent paragraphs, we
will determine the minimum value of inductance required
for our system and consider the trade−off of ripple current
vs. transient response.
In order to choose the minimum value of inductance, input
voltage, output voltage and output current must be known.
Most computer applications use reasonably well regulated
bulk power supplies so that, while the equations below
specify V
IN(MAX)
or V
IN(MIN)
, it is possible to use the
nominal value of V
IN
in these calculations with little error.
NCP1571
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12
Current in the inductor while operating in the continuous
current mode is defined as the load current plus ripple
current.
I
L
I
LOAD
I
RIPPLE
The ripple current waveform is triangular, and the current
is a function of voltage across the inductor, switch FET
on−time and the inductor value. FET on−time can be defined
as the product of duty cycle and switch frequency, and duty
cycle can be defined as a ratio of V
OUT
to V
IN
. Thus,
I
RIPPLE
(
V
IN
V
OUT
)
V
OUT
(
f
OSC
)(
L
)(
V
IN
)
Peak inductor current is defined as the load current plus
half of the peak current. Peak current must be less than the
maximum rated FET switch current, and must also be less
than the inductor saturation current. Thus, the maximum
output current can be defined as:
I
OUT(MAX)
I
SWITCH(MAX)
V
IN(MAX)
V
OUT
V
OUT
2

f
OSC

L

V
IN(MAX)
Since the maximum output current must be less than the
maximum switch current, the minimum inductance required
can be determined.
L
(MIN)
(
V
IN(MIN)
V
OUT
)
V
OUT
(
f
OSC
)(
I
SWITCH(MAX)
)(
V
IN(MIN)
)
This equation identifies the value of inductor that will
provide the full rated switch current as inductor ripple
current, and will usually result in inefficient system
operation. The system will sink current away from the load
during some portion of the duty cycle unless load current is
greater than half of the rated switch current. Some value
larger than the minimum inductance must be used to ensure
the converter does not sink current. Choosing larger values
of inductor will reduce the ripple current, and inductor value
can be designed to accommodate a particular value of ripple
current by replacing I
SWITCH(MAX)
with a desired value of
I
RIPPLE
:
L
(RIPPLE)
(
V
IN(MIN)
V
OUT
)
V
OUT
(
f
OSC
)(
I
RIPPLE
)(
V
IN(MIN)
)
However, reducing the ripple current will cause transient
response times to increase. The response times for both
increasing and decreasing current steps are shown below.
T
RESPONSE(INCREASING)
(
L
)(
I
OUT
)
(
V
IN
V
OUT
)
T
RESPONSE(DECREASING)
(
L
)(
I
OUT
)
(
V
OUT
)
Inductor value selection also depends on how much output
ripple voltage the system can tolerate. Output ripple voltage
is defined as the product of the output ripple current and the
output filter capacitor ESR.
Thus, output ripple voltage can be calculated as:
V
RIPPLE
ESR
C

I
RIPPLE
ESR
C

V
IN
V
OUT
V
OUT
f
OSC

L

V
IN
Finally, we should consider power dissipation in the
output inductors. Power dissipation is proportional to the
square of inductor current:
P
D
(I
2
L
)
(
ESR
L
)
The temperature rise of the inductor relative to the air
surrounding it is defined as the product of power dissipation
and thermal resistance to ambient:
T(inductor) (Ra)(P
D
)
Ra for an inductor designed to conduct 20 A to 30 A is
approximately 45°C/W. The inductor temperature is given as:
T(inductor) T(inductor) Tambient
V
CC
Bypass Filtering
A small RC filter should be added between module V
CC
and the V
CC
input to the IC. A 10 resistor and a 0.47 F
capacitor should be sufficient to ensure the controller IC does
not operate erratically due to injected noise, and will also
supply reserve charge for the onboard gate drivers.
Input Filter Capacitors
The input filter capacitors provide a charge reservoir that
minimizes supply voltage variations due to changes in current
flowing through the switch FETs. These capacitors must be
chosen primarily for ripple current rating.
Figure 24.
V
IN
V
OUT
I
IN(AVE)
I
RMS(CIN)
C
IN
CONTROL
INPUT
L
IN
L
OUT
C
OUT
Consider the schematic shown in Figure 24. The average
current flowing in the input inductor L
IN
for any given
output current is:
I
IN(AVE)
I
OUT
V
OUT
V
IN
Input capacitor current is positive into the capacitor when
the switch FETs are off, and negative out of the capacitor
when the switch FETs are on. When the switches are off,
I
IN(AVE)
flows into the capacitor. When the switches are on,
capacitor current is equal to the per−phase output current
minus I
IN(AVE)
. If we ignore the small current variation due
to the output ripple current, we can approximate the input
capacitor current waveform as a square wave. We can then
calculate the RMS input capacitor ripple current:
I
RMS(CIN)
I
2
IN(AVE)
V
OUT
V
IN
I
OUT
per phase I
IN(AVE)
2
I
2
IN(AVE)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

NCP1571DG

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Manufacturer:
ON Semiconductor
Description:
Switching Controllers Low Voltage Synchronous Buck
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