6.42
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
3
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
Figure 1. AC Test Load
*Including jig and scope capacitance.
DC Electrical Characteristics
(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC–0.2V)
AC Test Conditions
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
DC Electrical Characteristics
(VCC = 5.0V ± 10%)
2948 drw 03
480Ω
255Ω30pF*
DATA
OUT
5V
,
2948 drw 04
480Ω
255Ω5pF*
DATA
OUT
5V
.
Symbol Parameter Test Conditions
IDT71256SA
UnitMin. Max.
|I
LI
| Input Leakage Current V
CC
= Max., V
IN
=
GND to V
CC
___
5µA
|I
LO
| Output Leakage Current V
CC
= Max., CS = V
IH
, V
OUT
= GND to V
CC
___
5µA
V
OL
Output Low Voltage I
OL
= 8mA, V
CC
= Min.
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA, V
CC
= Min. 2.4
___
V
2948 tbl 05
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
Symbol Parameter 71256SA12 71256SA15 71256SA20 71256SA25 Unit
I
CC
Dynamic Operating Current
CS <
VIL, Outputs Open, VCC = Max., f = fMAX
(2)
160 150 145 145 mA
I
SB
Standby Power Supply Current (TTL Level)
CS >
VIH, Outputs Open, VCC = Max., f = fMAX
(2)
50 40 40 40 mA
I
SB1
Standby Power Supply Current (CMOS Level)
CS >
VHC, Outputs Open, VCC = Max., f = 0
(2)
,
V
IN < VLC or VIN > VHC
15 15 15 15 mA
2948 tbl 06
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
2948 tbl 07
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 7 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
2948 tbl 08