4
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%)
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
Symbol Parameter
71256SA12 71256SA15 71256SA20 71256SA25
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Read Cycle
t
RC
Read Cycle Time 12
____
15
____
20
____
25
____
ns
t
AA
Address Access Time
____
12
____
15
____
20
____
25 ns
t
ACS
Chip Select Access Time
____
12
____
15
____
20
____
25 ns
t
CL Z
(1 )
Chip Select to Output in Low-Z 4
____
4
____
4
____
4
____
ns
t
CHZ
(1 )
Chip Select to Output in High-Z 0 6 0 7 0 10 0 11 ns
t
OE
Output Enable to Output Valid
____
6
____
7
____
10
____
11 ns
t
OLZ
(1)
Output Enable to Output in Low-Z 0
____
0
____
0
____
0
____
ns
t
OHZ
(1 )
Output Disable to Output in High-Z 060608010ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
3
____
ns
t
PU
(1)
Chip Select to Power Up Time 0
____
0
____
0
____
0
____
ns
t
PD
(1)
Chip Deselect to Power Down Time
____
12
____
15
____
20
____
25 ns
Write Cycle
t
WC
Write Cycle Time 12
____
15
____
20
____
25
____
ns
t
AW
Address Valid to End-of-Write 9
____
10
____
15
____
20
____
ns
t
CW
Chip Select to End-of-Write 9
____
10
____
15
____
20
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 8
____
10
____
15
____
20
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 6
____
7
____
11
____
13
____
ns
t
DH
Data Hold Time 0
____
0
____
0
____
0
____
ns
t
OW
(1)
Output Active from End-of-Write 4
____
4
____
4
____
4
____
ns
t
WHZ
(1)
Write Enable to Output in High-Z 0 6 0 6 0 10 0 11 ns
2948 tbl 09