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CY7C1352G-133AXCT

P1-P3P4-P6P7-P9P10-P12P13-P13
PRELIMINARY
CY7C1352G
Document #: 38-05514 Rev. *B Page 7 of 13
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage on V
DD
Relative to GND.........−0.5V to +4.6V
DC Voltage Applied to Outputs
in tri-state..................................................−0.5V to V
DDQ
+ 0.5V
DC Input Voltage ...................................... −0.5V to V
DD
+ 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Ambient
Temperature (T
A
)V
DD
V
DDQ
Com’l 0°C to +70°C 3.3V –5%/+10% 2.5V –5%
to V
DD
Ind’l –40°C to +85°C
Electrical Characteristics Over the Operating Range
[9, 10]
Parameter Description Test Conditions Min. Max. Unit
V
DD
Power Supply Voltage 3.135 3.6 V
V
DDQ
I/O Supply Voltage 2.375 V
DD
V
V
OH
Output HIGH Voltage for 3.3V I/O, I
OH
= –4.0 mA 2.4 V
for 2.5V I/O, I
OH
= –1.0 mA 2.0 V
V
OL
Output LOW Voltage for 3.3V I/O, I
OL
= 8.0 mA 0.4 V
for 2.5V I/O, I
OL
= 1.0 mA 0.4 V
V
IH
Input HIGH Voltage
[9]
for 3.3V I/O 2.0 V
DD
+ 0.3V V
for 2.5V I/O 1.7 V
DD
+ 0.3V V
V
IL
Input LOW Voltage
[9]
for 3.3V I/O –0.3 0.8 V
for 2.5V I/O –0.3 0.7 V
I
X
Input Load Current except ZZ
and MODE
GND ≤ V
I
≤ V
DDQ
−55µA
Input Current of MODE Input = V
SS
−30 µA
Input = V
DD
5 µA
Input Current of ZZ Input = V
SS
−5 µA
Input = V
DD
30 µA
I
OZ
Output Leakage Current GND ≤ V
I
≤ V
DDQ,
Output Disabled −55µA
I
DD
V
DD
Operating Supply
Current
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
4-ns cycle, 250 MHz 325 mA
5-ns cycle, 200 MHz 265 mA
6-ns cycle, 166 MHz 240 mA
7.5-ns cycle,133MHz 225 mA
I
SB1
Automatic CE
Power-Down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
≥ V
IH
or V
IN
≤ V
IL
f = f
MAX
= 1/t
CYC
4-ns cycle, 250 MHz 120 mA
5-ns cycle, 200 MHz 110 mA
6-ns cycle, 166 MHz 100 mA
7.5-ns cycle,133MHz 90 mA
I
SB2
Automatic CE
Power-down
Current—CMOS Inputs
V
DD
= Max, Device Deselected,
V
IN
≤ 0.3V or
V
IN
> V
DDQ
– 0.3V, f = 0
All speeds 40 mA
Shaded areas contain advance information.
Notes:
9. Overshoot: V
IH
(AC) < V
DD
+1.5V (Pulse width less than t
CYC
/2), undershoot: V
IL
(AC)> –2V (Pulse width less than t
CYC
/2).
10. T
Power-up
: Assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
PRELIMINARY
CY7C1352G
Document #: 38-05514 Rev. *B Page 8 of 13
I
SB3
Automatic CE
Power-down
Current—CMOS Inputs
V
DD
= Max, Device Deselected,
or V
IN
≤ 0.3V or V
IN
> V
DDQ
–
0.3V
f = f
MAX
= 1/t
CYC
4-ns cycle, 250 MHz 105 mA
5-ns cycle, 200 MHz 95 mA
6-ns cycle, 166 MHz 85 mA
7.5-ns cycle,133 MHz 75 mA
I
SB4
Automatic CE
Power-down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
≥ V
IH
or V
IN
≤ V
IL
, f = 0
All speeds 45 mA
Thermal Resistance
[11]
Parameter Description Test Conditions TQFP Package Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA / JESD51.
30.32 °C/W
Θ
JC
Thermal Resistance
(Junction to Case)
6.85 °C/W
Capacitance
[11]
Parameter Description Test Conditions Max. Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz,
V
DD
= 3.3V,
V
DDQ
= 3.3V
5pF
C
CLK
Clock Input Capacitance 5 pF
C
I/O
Input/Output Capacitance 5 pF
AC Test Loads and Waveforms
Note:
11. Tested initially and after any design or process changes that may affect these parameters.
Electrical Characteristics Over the Operating Range
[9, 10]
(continued)
Parameter Description Test Conditions Min. Max. Unit
1ns
OUTPUT
R = 317Ω
R = 351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50Ω
Z
0
= 50Ω
V
T
= 1.5V
3.3V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
≤ 1 ns
≤ 1 ns
(c)
OUTPUT
R = 1667Ω
R =1538Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
R
L
= 50Ω
Z
0
= 50Ω
V
T
= 1.25V
2.5V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
≤ 1 ns
≤ 1 ns
(c)
3.3V I/O Test Load
2.5V I/O Test Load
PRELIMINARY
CY7C1352G
Document #: 38-05514 Rev. *B Page 9 of 13
Switching Characteristics Over the Operating Range
[16, 17]
Parameter Description
250 MHz 200 MHz 166 MHz 133 MHz
Unit
Min. Max Min. Max Min. Max Min. Max
t
POWER
V
DD
(typical) to the first Access
[12]
1 111ms
Clock
t
CYC
Clock Cycle Time 4.0 5.0 6.0 7.5 ns
t
CH
Clock HIGH 1.7 2.0 2.5 3.0 ns
t
CL
Clock LOW 1.7 2.0 2.5 3.0 ns
Output Times
t
CO
Data Output Valid After CLK Rise 2.6 2.8 3.5 4.0 ns
t
DOH
Data Output Hold After CLK Rise 1.0 1.0 1.5 1.5 ns
t
CLZ
Clock to Low-Z
[13, 14, 15]
0 000ns
t
CHZ
Clock to High-Z
[13, 14, 15]
2.6 2.8 3.5 4.0 ns
t
OEV
OE LOW to Output Valid 2.6 2.8 3.5 4.0 ns
t
OELZ
OE LOW to Output Low-Z
[13, 14, 15]
0 000ns
t
OEHZ
OE HIGH to Output High-Z
[13, 14, 15]
2.6 2.8 3.5 4.0 ns
Set-up Times
t
AS
Address Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns
t
ALS
ADV/LD Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns
t
WES
GW, BW
[A:B]
Set-Up Before CLK Rise 1.2 1.2 1.5 1.5 ns
t
CENS
CEN Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns
t
DS
Data Input Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns
t
CES
Chip Enable Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns
Hold Times
t
AH
Address Hold After CLK Rise 0.3 0.5 0.5 0.5 ns
t
ALH
ADV/LD Hold after CLK Rise 0.3 0.5 0.5 0.5 ns
t
WEH
GW, BW
[A:B]
Hold After CLK Rise
0.3 0.5 0.5 0.5 ns
t
CENH
CEN Hold After CLK Rise 0.3 0.5 0.5 0.5 ns
t
DH
Data Input Hold After CLK Rise 0.3 0.5 0.5 0.5 ns
t
CEH
Chip Enable Hold After CLK Rise 0.3 0.5 0.5 0.5 ns
Shaded areas contain advance information.
Notes:
12.This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above V
DD
minimum initially before a read or write operation
can be initiated.
13. t
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
14.At any given voltage and temperature, t
OEHZ
is less than t
OELZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve tri-state prior to Low-Z under the same system conditions.
15.This parameter is sampled and not 100% tested.
16.Timing reference level is 1.5V when V
DDQ
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
17.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
P1-P3P4-P6P7-P9P10-P12P13-P13

CY7C1352G-133AXCT

Mfr. #:
Buy CY7C1352G-133AXCT
Manufacturer:
Cypress Semiconductor
Description:
SRAM 256Kx18 3.3V NoBL Sync PL SRAM COM
Lifecycle:
New from this manufacturer.
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