SCE5741Q Datasheet SCE5743P, SCE5741P, SCE5741Q | P4-P6

SCE5740, SCE5741, SCE5742, SCE5743, SCE5744, SCE5745

2006-03-30 4

Input/Output Circuits

Figures „Inputs“ and „Clock I/O“ show the input and output resis-

tor/diode networks used for ESD protection and to eliminate sub-

strate latch-up caused by input voltage over/under shoot.

Inputs

Clock I/O (SCE574X only)

Electrical Characteristics (over operating temperature)

Parameter Min. Typ. Max. Units Conditions

4.5 5.0 5.5 V —

(Power Down)

1) 2)

— — 50 µA V

=5.0 V, all inputs=0 V or V

4 digits 20 dots/character

90 115 130 mA V

=5.0 V, “#” displayed in all 4 digits

at 100% brightness at 25

°C

Input current — — –10 µA V

=5.0 V, V

=0 (all inputs)

Input current

—

— 10 µA V

=5.0 V (all inputs)

3.5 — — V V

=4.5 V to 5.5 V

— — 1.5 V V

=4.5 V to 5.5 V

Row Multiplex Rate 375 768 1086 Hz —

JC-pin

— — 45 °C/W —

Notes:

Unused inputs must be tied high.

External oscillator must be stopped.

Peak current

x I

CC.

Electrical Characteristics for SCE574x only

Parameter Min. Typ. Max. Units Conditions

(CLK I/O) — –28 — mA V

=4.5 V, V

=2.4 V

(CLK I/O) — 23 — mA V

=4.5 V, V

=0.4 V

ext

External Clock Input

Frequency

120 — 3 MHz V

=5.0 V, CLKSEL=0

osc

Internal Clock Input

Frequency

120 — 347 kHz V

=5.0 V, CLKSEL=1

Clock I/O Bus Loading — — 240 pF —

Clock Out Rise Time — — 500 ns V

=4.5 V, V

=2.4 V

Clock Out Fall Time — — 500 ns V

=4.5 V, V

=0.4 V

IDCD5021

GND

1 k

ΩInput

1 KΩ

GND

input/output

SCE5740, SCE5741, SCE5742, SCE5743, SCE5744, SCE5745

2006-03-30 5

Timing Diagram—Data Write Cycle

Timing Diagram—Instruction Cycle

Switching Specifications

(over operating temperature range and V

=4.5 V to 5.5 V)

Symbol Description Min. Units Symbol Description Min. Units

Reset Active Time 600 ns T

SDCW

Clock Width 70 ns

LDS

Load Setup Time 50 ns T

LDH

Load Hold Time 0 ns

Data Setup Time 50 ns T

Data Hold Time 25 ns

SDCLK

Clock Period 200 ns T

Total Write Time 2.2 µs

Time Between Loads 600 ns

Note:

SDCW

is the minimum time the SDCLK may be low or high.

The SDCLK period must be a minimum of 200 ns.

SDCLK

SDCW

DATA

LOAD

LDS

LDH

LOAD

DATA

SDCLK

SCE5740, SCE5741, SCE5742, SCE5743, SCE5744, SCE5745

2006-03-30 6

Top View

Dot Matrix Format

Pin Assignment

Pin Function Pin Function

1 V

14 CLK SELECT

2 LOAD 13 no pin

3 DATA 12 no pin

4 no connection 11 no pin

5 SDCLK 10 no pin

6 RST 9 no pin

7 GND 8 CLK I/O

IDPA5105

Digit 0 Digit 1 Digit 2 Digit 3

Pins17

Pins14 8

Dimensions in inches (mm)

Tolerance: ±0.25 (0.010)

1.14 (0.045) typ.

4.45 (0.175)

0.23 (0.009) typ. 1.09 (0.043) typ.

C1 C2

IDOD5013

6.86 (0.270)

C3 C4

Pin Definitions

Pin Function Definitions

1 V

Power supply

2 LOAD Low input enables data clocking into 8-bit

serial shift register. When LOAD goes high,

the contents of 8-bit serial Shift Register will

be decoded.

3 DATA Serial data input

4 N/C no connection

5 SDCLK for loading data into the 8-bit serial data

6 RST Asynchronous input, when low clears the

Multiplex Counter, Control Word Register,

User RAM and Data Register. Control Word

display will be blank.

7 GND Supply ground

8 CLK I/O Outputs master clock or inputs external clock.

9 N/P No pins

10 N/P No pins

11 N/P No pins

12 N/P No pins

13 N/P No pins

14 CLKSEL H=internal clock, L=external clock

Display Column and Row Format

C0 C1 C2 C3 C4

Row 0 1 1 1 1 1

Row 1 0 0 1 0 0

Row 2 0 0 1 0 0

Row 3 0 0 1 0 0

Row 4 0 0 1 0 0

Row 5 0 0 1 0 0

Row 6 0 0 1 0 0

1= Display dot „ON“

0=Display dot „OFF“

Column Data Ranges

Row 0 00H to 1FH Row 4 00H to LFH

Row 1 00H to LFH Row 5 00H to LFH

Row 2 00H to LFH Row 6 00H to LFH

Row 3 00H to LFH

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

SCE5741Q

Mfr. #:

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DISPLAY 4CHAR 5X7 SER YLW QSIP

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SCE5741Q

SCE5741Q

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