SCE5740, SCE5741, SCE5742, SCE5743, SCE5744, SCE5745
2006-03-30 7
Block Diagram
Operation of the SCE574x
The SCE574x display consists of a CMOS IC containing control
logic and drivers for four 5 x 7 characters. These components are
assembled in a compact plastic package.
Individual LED dot addressability allows the user great freedom in
creating special characters or mini-icons.
The serial data interface provides a highly efficient interconnection
between the display and the mother board. The SCE574x requires
only three lines as compared to 14 lines for an equivalent four
character parallel input part.
The on-board CMOS IC is the electronic heart of the display. The
IC accepts decoded serial data, which is stored in the internal
RAM. Asynchronously the RAM is read by the character multi-
plexer at a strobe rate that results in a flicker free display. Figure
„Block Diagram“ (page 7) shows the three functional areas of the
IC. These include: the input serial data register and control logic, a
140 bits two port RAM, and an internal multiplexer/display driver.
The following explains how to format the serial data to be loaded
into the display. The user supplies a string of bit mapped decoded
characters. The contents of this string is shown in Figure „Loading
Serial Character Data a“ (page 8). Figure „Loading Serial Charac-
ter Data b“ (page 8) shows that each character consist of eight 8
bit words. The first word encodes the display character location
and the succeeding five bytes are row data. The row data repre-
sents the status (On, Off) of individual column LEDs. Figure „Load-
ing Serial Character Data c“ (page 8) shows that each 8 bit word is
formatted to represent Column Data or Character Address.
Figure „Loading Serial Character Data d“ (page 8) shows the
sequence for loading the bytes of data. Bringing the LOAD line low
enables the serial register to accept data. The shift action occurs
on the low to high transition of the serial data clock (SDCLK). The
least significant bit (D0) is loaded first. After eight clock pulses the
LOAD line is brought high. With this transition the OPCODE is
decoded. The decoded OPCODE directs D4–D0 to be latched in
the Character Address register, stored in the RAM as Column
data, or latched in the Control Word register. The control IC
requires a minimum 600 ns delay between successive byte loads.
IDBD5063
Memory
Y Address Decode
User RAM
Drivers
Digit
Column
0 to 4
7 x 20 bits
X Address Decode
3-bit Address Register
6-bit Control
Word Register
Control Word Logic
Column 0 to 20
0
Display
123
and Row Drivers
Row Control Logic
Counter
764
Counter
OSC
8-bit Serial Register
Rows
0 to 6
MUX
Rate
DATA
SDCLK
LOAD
CLKSEL
CLK I/O
RST
