CY25403/CY25423/CY25483
Three PLL Programmable Clock Generator with
Spread Spectrum
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-12564 Rev. *C Revised August 10, 2009
Features
■ Three fully integrated phase locked loops (PLLs)
■ Input frequency range
❐ External crystal: 8 to 48 MHz
❐ External reference: 8 to 166 MHz clock
■ Reference Clock input voltage range
❐ 2.5V, 3.0V, and 3.3V for CY25483
❐ 1.8V for CY25403 and CY25423
■ Wide operating output frequency range
❐ 3 to 166 MHz
■ Programmable Spread Spectrum with Center and Down
Spread option and Lexmark and Linear modulation profiles
■ VDD supply voltage options:
❐ 2.5V, 3.0V, and 3.3V for CY25403 and CY25483
❐ 1.8V for CY25423
■ Selectable output clock voltages independent of VDD supply:
❐ 2.5V, 3.0V, and 3.3V for CY25403 and CY25483
❐ 1.8V for CY25423
■ Frequency Select feature with option to select four different
frequencies
■ Power Down, Output Enable, and SS ON/OFF controls
■ Low jitter, high accuracy outputs
■ Ability to synthesize nonstandard frequencies with
Fractional-N capability
■ Three clock outputs with Programmable drive strength
■
Glitch-free outputs while frequency switching
■ 8-pin SOIC package
■ Commercial and Industrial temperature ranges
Benefits
■ Multiple high performance PLLs allow synthesis of unrelated
frequencies
■ Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
■ Application specific Programmable EMI reduction using
Spread Spectrum for clocks
■ Programmable PLLs for system frequency margin tests
■ Meets critical timing requirements in complex system
designs
■ Suitability for PC, consumer, portable, and networking appli-
cations
■ Capable of Zero PPM frequency synthesis error
■ Uninterrupted system operation during clock frequency
switch
■ Application compatibility in standard and low power systems
OSC PLL1
PLL3
(SS)
CLK3
(SS)
CLK2
(No SS
CLK1
(SS)
Crossbar
Switch
FS1
SSON
XOUT
XIN/
EXCLKIN
PD#/OE
PLL 2
(SS)
FS0
MUX
and
Control
Logic
Output
Dividers
and
Drive
Strength
Control
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