Document #: 001-12564 Rev. *C Page 4 of 10
General Description
3 Configurable PLLs
The CY25403, CY25483 and CY25423 have three program-
mable PLLs that can be used to generate output frequencies
ranging from 3 to 166 MHz. The advantage of having three PLLs
is that a single device generates up to three independent
frequencies from a single crystal.
Input Reference Clocks
The input reference clock can be either a crystal or a clock signal,
for CY25403 and CY25423 while just a clock signal for CY25483.
The input frequency range for crystal (XIN) is 8 MHz to 48 MHz
and that for external reference clock (EXCLKIN) is 8 MHz to 166
MHz. The voltage range of the reference clock input for CY25483
is 2.5V/3.0V/3.3V while that for CY25403 and CY25423 is 1.8V.
This gives user an option for this device to be compatible for
different input clock voltage levels in the system.
VDD Power Supply Options
These devices have programmable power supply options. The
CY25403/CY25483 is a high voltage part that can be
programmed to operate at any voltage 2.5V, 3.0V, or 3.3V while
CY25423 is a low voltage part that can operate at 1.8V.
Output Source Selection
These devices have programmable input sources for each of its
clock outputs. There are four available clock sources and these
clock sources are: XIN/EXCLKIN, PLL1, PLL2, and PLL3.
Output clock source selection is done by using four out of four
crossbar switch. Thus, any one of these four available clock
sources can be arbitrarily selected for the clock outputs. This
gives user a flexibility to have up to three independent clock
outputs.
Spread Spectrum Control
Two of the three PLLs (PLL2 and PLL3) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress proprietary PLL and Spread Spectrum Clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off using a
multifunction control pin (CLK3/SSON). It can be programmed to
either center spread range from ±0.125% to ±2.50% or down
spread range from –0.25% to –5.0% with Lexmark or Linear
profile.
Frequency Select
Each PLL can be programmed for up to four different
frequencies. There are two multifunction programmable pins,
CLK2/FS0 and PD#/OE/FS1 which if programmed as frequency
select inputs, can be used to select among these arbitrarily
programmed frequency settings. Each output has program-
mable output divider options.
Glitch-Free Frequency Switch
When the frequency select pin, FS(1:0) is used to switch
frequency, the outputs are glitch-free provided frequency is
switched using output dividers. This feature enables uninter-
rupted system operation while clock frequency is being switched.
PD#/OE Mode
Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to
operate as either frequency select (FS1), power down (PD#) or
output enable (OE) mode. PD# is a low-true input. If activated it
shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings.
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 5). Individual
clock outputs can be programmed to be sensitive to this OE pin.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 4 shows the typical rise
and fall times for different drive strength settings.
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
device, CY25403, CY25483 and CY25423 can be custom
programmed to any desired frequencies and listed features. For
customer specific programming, please contact local Cypress
Field Application Engineer (FAE) or sales representative.
Table 4. Output Drive Strength
Output Drive Strength
Rise/Fall Time (ns)
(Typical Value)
Low 6.8
Mid Low 3.4
Mid High 2.0
High 1.0
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