Table 6: Component-to-Module DQ Map (Continued)
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
U11 0 9 18
1 10 23
2 8 16
3 11 25
4 12 160
5 15 169
6 13 162
7 14 167
8GB (x72, ECC, SR) 288-Pin DDR4 MiniRDIMM
DQ Map
CCMTD-341111752-10427
asf9c1gx72pkiz.pdf - Rev. D 1/18 EN
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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Functional Block Diagram
Figure 2: Functional Block Diagram
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U6
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U11
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U9
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
U2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U10
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
U3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
CS0_n
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
DQS0_t
DQS0_c
TDQS0_t
TDQS0_c
U4
VREFCA
VSS
DDR4 SDRAM, Register
DDR4 SDRAM, Register
VDD
Control, command and
address termination
VDDSPD
SPD EEPROM/Temp Sensor,
Register
VTT
DDR4 SDRAM, Register
DDR4 SDRAM
VPP
A/B-CS0_n, A/B-BA[1:0]A/B-BG[1:0],
A/B-ACT_n, A/B-A[17, 13:0], A/B-RAS_n/A16,
A/B-CAS_n/A15, A/B-WE_n/A14,
A/B-CKE0, A/B-ODT0
CK[1:0]_t
CK[1:0]_c
Command, control, address, and clock line terminations:
DDR4
SDRAM
VTT
DDR4
SDRAM
VDD
U5
A0
SPD EEPROM/
Temperature
sensor
A1 A2
SA0
SA1
SDA
SCL
EVT
EVENT_n
CS0_n
BA[1:0]
BG[1:0]
ACT_n
A[17, 13:0]
RAS_n/A16
CAS_n/A15
WE_n/A14
CKE0
ODT0
PAR_IN
ALERT_CONN_N
A/B-CS0_n: Rank 0
A/B-BA[1:0]: DDR4 SDRAMs
A/B-BG[1:0]: DDR4 SDRAMs
A/B-ACT_n: DDR4 SDRAMS
A/B-A[17,13:0]: DDR4 SDRAMs
A/B-RAS_n/A16: DDR4 SDRAMs
A/B-CAS_n/A15: DDR4 SDRAMs
A/B-WE_n/A14: DDR4 SDRAMs
A/B-CKE0: Rank 0
A/B-ODT0: Rank 0
A/B-PAR: DDR4 SDRAMs
ALERT_DRAM: DDR4 SDRAMs
R
E
G
I
S
T
E
R
&
P
L
L
RESET_CONN
CK[1:0]_c
DDR4 SDRAMs
RESET_DRAM: DDR4 SDRAMs
CK[1:0]_t
ZQ
VSS
SA2
TDQS_c DM_n/ CS_n DQS_t DQS_c
DBI_n/
TDQS_t
TDQS_c DM_n/ CS_n DQS_t DQS_c
DBI_n/
TDQS_t
TDQS_c DM_n/ CS_n DQS_t DQS_c
DBI_n/
TDQS_t
TDQS_c DM_n/ CS_n DQS_t DQS_c
DBI_n/
TDQS_t
TDQS_c DM_n/ CS_n DQS_t DQS_c
DBI_n/
TDQS_t
TDQS_c DM_n/ CS_n DQS_t DQS_c
DBI_n/
TDQS_t
TDQS_c DM_n/ CS_n DQS_t DQS_c
DBI_n/
TDQS_t
TDQS_c DM_n/ CS_n DQS_t DQS_c
DBI_n/
TDQS_t
TDQS_c DM_n/ CS_n DQS_t DQS_c
DBI_n/
TDQS_t
DQS4_t
DQS4_c
TDQS4_t
TDQS4_c
DQS1_t
DQS1_c
TDQS1_t
TDQS1_c
DQS2_t
DQS2_c
TDQS2_t
TDQS2_c
DQS3_t
DQS3_c
TDQS3_t
TDQS3_c
DQS8_t
DQS8_c
TDQS8_t
TDQS8_c
DQS5_t
DQS5_c
TDQS5_t
TDQS5_c
DQS6_t
DQS6_c
TDQS6_t
TDQS6_c
DQS7_t
DQS7_c
TDQS7_t
TDQS7_c
SA0
SA1
SA2
SCL
SDA
CK0_t
CK0_c
CK1_t
CK1_c
Note:
1. The ZQ ball on each DDR4 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.
8GB (x72, ECC, SR) 288-Pin DDR4 MiniRDIMM
Functional Block Diagram
CCMTD-341111752-10427
asf9c1gx72pkiz.pdf - Rev. D 1/18 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
General Description
High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with two or four internal
memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM
devices have four internal bank groups consisting of four memory banks each, provid-
ing a total of 16 banks. 16-bit-wide DDR4 SDRAM devices have two internal bank
groups consisting of four memory banks each, providing a total of eight banks. DDR4
SDRAM modules benefit from DDR4 SDRAM's use of an 8n-prefetch architecture with
an interface designed to transfer two data words per clock cycle at the I/O pins. A single
READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bit-
wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit-
wide, one-half-clock-cycle data transfers at the I/O pins.
DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data
and CK_t and CK_c to capture commands, addresses, and control signals. Differential
clocks and data strobes ensure exceptional noise immunity for these signals and pro-
vide precise crossing points to capture input signals.
Fly-By Topology
DDR4 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, com-
mand, and address buses have been routed in a fly-by topology, where each clock, con-
trol, command, and address pin on each DRAM is connected to a single trace and ter-
minated (rather than a tree structure, where the termination is off the module near the
connector). Inherent to fly-by topology, the timing skew between the clock and DQS sig-
nals can be easily accounted for by using the write-leveling feature of DDR4.
Module Manufacturing Location
Micron Technology manufactures modules at sites world-wide. Customers may receive
modules from any of the following manufacturing locations:
Table 7: DRAM Module Manufacturing Locations
Manufacturing Site Location Country of Origin Specified on Label
Boise, USA USA
Aguadilla, Puerto Rico Puerto Rico
Xian, China China
Singapore Singapore
8GB (x72, ECC, SR) 288-Pin DDR4 MiniRDIMM
General Description
CCMTD-341111752-10427
asf9c1gx72pkiz.pdf - Rev. D 1/18 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.

MTA9ASF1G72PKIZ-2G6B1

Mfr. #:
Manufacturer:
Micron
Description:
MODULE DDR4 8GB MINIRDIMM
Lifecycle:
New from this manufacturer.
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