Clock operations M48T129V, M48T129Y
14/28 Doc ID 5710 Rev 5
3.5 Calibrating the clock
The M48T129Y/V is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are factory calibrated at 25 °C and tested for accuracy. Clock
accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25 °C, which
equates to about ±1.53 minutes per month (see Figure 8 on page 15). When the calibration
circuit is properly employed, accuracy improves to better than +1/–2 ppm at
25 °C. The oscillation rate of crystals changes with temperature. The M48T129Y/V design
employs periodic counter correction. The calibration circuit adds or subtracts counts from
the oscillator divider circuit at the divide by 256 stage, as shown in Figure 9 on page 15.
The number of times pulses are blanked (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five calibration bits found in the
control register. Adding counts speeds the clock up, subtracting counts slows the clock
down. The calibration bits occupy the five lower order bits (D4-D0) in the control register
1FFF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit
D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration
occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened by 256 oscillator cycles.
If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be
modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each
calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every
125, 829, 120 actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per
calibration step in the calibration register. Assuming that the oscillator is running at exactly
32,768Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35
seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month.
Figure 9 on page 15 illustrates a TIMEKEEPER
®
calibration waveform.
Two methods are available for ascertaining how much calibration a given M48T129Y/V may
require. The first involves setting the clock, letting it run for a month and comparing it to a
known accurate reference and recording deviation over a fixed period of time.
Calibration values, including the number of seconds lost or gained in a given period, can be
found in the application note “AN934, Timekeeper calibration.”
This allows the designer to give the end user the ability to calibrate the clock as the
environment requires, even if the final product is packaged in a non-user serviceable
enclosure. The designer could provide a simple utility that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use
of the IRQ
/FT pin. The pin will toggle at 512 Hz, when the stop bit (ST, D7 of 1FFF9h) is '0,'
the frequency test bit (FT, D6 of 1FFFCh) is '1,' the alarm flag enable bit (AFE, D7 of
1FFF6h) is '0,' and the watchdog steering bit (WDS, D7 of 1FFF7h) is '1' or the watchdog
register (1FFF7h = 0) is reset.
Note: A 4 second settling time must be allowed before reading the 512 Hz output.
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (WR001010) to be loaded into the calibration byte
for correction. Note that setting or changing the calibration byte does not affect the
frequency test output frequency.
The IRQ
/FT pin is an open drain output which requires a pull-up resistor for proper
operation. A 500-10 kΩ resistor is recommended in order to control the rise time. The FT bit
is cleared on power-up.
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