M48T129Y-70PM1 Datasheet M48T129V-85PM1, M48T129Y-70PM1 | P16-P18

Clock operations M48T129V, M48T129Y

16/28 Doc ID 5710 Rev 5

3.6 Setting the alarm clock

Registers 1FFF6h-1FFF2h contain the alarm settings. The alarm can be configured to go off

at a prescribed time on a specific month, date, hour, minute, or second or repeat every

month, day, hour, minute, or second. It can also be programmed to go off while the

M48T129Y/V is in the battery back-up to serve as a system wake-up call.

Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 6 on page 16 shows

the possible configurations. Codes not listed in the table default to the once per second

mode to quickly alert the user of an incorrect alarm setting.

Note: User must transition address (or toggle chip enable) to see flag bit change.

When the clock information matches the alarm clock settings based on the match criteria

defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set, the

alarm condition activates the IRQ

/FT pin. To disable alarm, write ’0’ to the alarm date

/FT output is cleared by a READ to the flags register as

shown in Figure 10 A subsequent READ of the flags register is necessary to see that the

value of the alarm flag has been reset to '0.'

The IRQ

/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if

an alarm occurs and both ABE (alarm in battery backup mode enable) and AFE are set. The

ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up

will only set AF. The user can read the flag register at system boot-up to determine if an

alarm was generated while the M48T129Y/V was in the deselect mode during power-up.

Figure 11 on page 17 illustrates the backup mode alarm timing.

Figure 10. Alarm interrupt reset waveform

Table 6. Alarm repeat mode

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm activated

1 1 1 1 1 Once per second

11110Once per minute

1 1 1 0 0 Once per hour

11000Once per day

10000Once per month

00000Once per year

AI02581

AD0-AD7

ACTIVE FLAG BIT

ADDRESS 1FF0h

IRQ/FT

HIGH-Z

15ns Min

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M48T129V, M48T129Y Clock operations

Doc ID 5710 Rev 5 17/28

Figure 11. Backup mode alarm waveforms

3.7 Watchdog timer

The watchdog timer can be used to detect an out-of-control microprocessor. The user

programs the watchdog timer by setting the desired amount of time-out into the watchdog

order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1

second, and 11 = 4 seconds. The amount of time-out is then determined to be the

multiplication of the five-bit multiplier value with the resolution. (For example: writing

00001110 in the watchdog register = 3*1 or 3 seconds).

Note: Accuracy of timer is a function of the selected resolution.

If the processor does not reset the timer within the specified period, the M48T129Y/V sets

the WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset.

WDF is reset by reading the flags register (address 1FFF0h). The most significant bit of the

watchdog register is the watchdog steering bit (WDS). When set to a '0,' the watchdog will

activate the IRQ

/FT pin when timed-out. When WDS is set to a '1,' the watchdog will output

a negative pulse on the RST

pin for 40 to 200 ms. The watchdog register and the FT bit will

reset to a '0' at the end of a watchdog time-out when the WDS bit is set to a '1.'

The watchdog timer can be reset by two methods:

1. a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI);

2. the microprocessor can perform a WRITE of the watchdog register.

The time-out period then starts over. The WDI pin should be tied to V

if not used. The

watchdog will be reset on each transition (edge) seen by the WDI pin. In the order to

perform a software reset of the watchdog timer, the original time-out period can be written

into the watchdog register, effectively restarting the count-down cycle.

AI01678C

IRQ/FT

HIGH-Z

PFD

(max)

PFD

(min)

AFE bit in Interrupt Register

AF bit in Flags Register

HIGH-Z

tREC

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Clock operations M48T129V, M48T129Y

18/28 Doc ID 5710 Rev 5

Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt,

a value of “00h” needs to be written to the watchdog register in order to clear the IRQ

/FT

pin. This will also disable the watchdog function until it is again programmed correctly. A

READ of the flags register will reset the watchdog flag (bit D7; register 1FFF0h).

The watchdog function is automatically disabled upon power-down and the watchdog

/FT pin and the

frequency test function is activated, the watchdog or alarm function prevails and the

frequency test function is denied.

3.8 Power-on reset

The M48T129Y/V continuously monitors V

. When V

falls to the power fail detect trip

point, the RST

pulls low (open drain) and remains low on power-up for t

REC

after V

passes V

PFD

(max). The RST pin is an open drain output and an appropriate pull-up resistor

to V

should be chosen to control the rise time.

3.9 Battery low warning

The M48T129Y/V automatically performs battery voltage monitoring upon power-up and at

factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit

D4 of flags register 1FFF0h, will be asserted if the battery voltage is found to be less than

approximately 2.5 V.

If a battery low is generated during a power-up sequence, this indicates that the battery is

below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM.

Data should be considered suspect and verified as correct.

If a battery low indication is generated during the 24-hour interval check, this indicates that

the battery is near end of life. However, data is not compromised due to the fact that a

nominal V

is supplied.

The M48T129Y/V only monitors the battery when a nominal V

is applied to the device.

Thus applications which require extensive durations in the battery back-up mode should be

powered-up periodically (at least once every few months) in order for this technique to be

beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon

power-up via a checksum or other technique.

3.10 Initial power-on defaults

Upon application of power to the device, the following register bits are set to a '0' state:

WDS, BMB0-BMB4, RB0,RB1, AFE, ABE, W, R and FT.

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M48T129Y-70PM1

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Manufacturer:

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IC RTC CLK/CALENDAR PAR 32-DIP

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