8525BG www.icst.com/products/hiperclocks.html REV. C AUGUST 1, 2007
8
ICS8525
LOW SKEW, 1-TO-4
LVCMOS-TO-LVHSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8525.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8525 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 50mA = 173.25mW
• Power (outputs)
MAX
= 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 4 x 32.8mW = 131.2mW
Total Power
_MAX
(3.465V, with all outputs switching) = 173.25mW + 131.2mW = 304.45mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj = θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming a
moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.305W * 66.6°C/W = 90.3°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6. THERMAL RESISTANCE
θθ
θθ
θ
JA
FOR 20-PIN TSSOP, FORCED CONVECTION
