LTC3703
13
3703fc
applicaTions inForMaTion
The oscillator can also be synchronized to an external
clock applied to the MODE/SYNC pin with a frequency in
the range of 100kHz to 600kHz (refer to the MODE/SYNC
Pin section for more details). In this synchronized mode,
pulse-skip mode operation is disabled. The clock high level
must exceed 2V for at least 25ns. As shown in Figure 8,
the top MOSFET turn-on will follow the rising edge of the
external clock by a constant delay equal to one-tenth of
the cycle period.
3703 F08
2V TO 10V
MODE/
SYNC
TG
I
L
t
MIN
= 25ns
0.8T
0.1T
D = 40%
T T = 1/f
O
Figure 8. MODE/SYNC Clock Input and Switching
Waveforms for Synchronous Operation
Inductor
The inductor in a typical LTC3703 circuit is chosen for a
specific ripple current and saturation current. Given an
input voltage range and an output voltage, the inductor
value and operating frequency directly determine the ripple
current. The inductor ripple current in the buck mode is:
I
L
=
V
OUT
(f)(L)
1–
V
OUT
V
IN
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Thus highest efficiency operation is obtained at
low frequency with small ripple current. To achieve this
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
between 20% and 40% of I
O(MAX)
. Note that the largest
ripple current occurs at the highest V
IN
. To guarantee that
ripple current does not exceed a specified maximum, the
inductor in buck mode should be chosen according to:
L
V
OUT
f I
L(MAX)
1
V
OUT
V
IN(MAX)
The inductor also has an affect on low current operation
when pulse-skip mode operation is enabled. The frequency
begins to decrease when the output current drops below
the average inductor current at which the LTC3703 is
operating at its t
ON(MIN)
in discontinuous mode (see
Figure 6). Lower inductance increases the peak inductor
current that occurs in each minimum on-time pulse and
thus increases the output current at which the frequency
starts decreasing.
Power MOSFET Selection
The LTC3703 requires at least two external N-channel
power MOSFETs, one for the top (main) switch and one or
more for the bottom (synchronous) switch. The number,
type andon” resistance of all MOSFETs selected take into
account the voltage step-down ratio as well as the actual
position (main or synchronous) in which the MOSFET will
be used. A much smaller and much lower input capacitance
MOSFET should be used for the top MOSFET in applica-
tions that have an output voltage that is less than 1/3 of
the input voltage. In applications where V
IN
>> V
OUT
, the
top MOSFETs’ “on” resistance is normally less important
for overall efficiency than its input capacitance at operating
frequencies above 300
kHz. MOSFET manufacturers have
designed special purpose devices that provide reason-
ably lowon” resistance with significantly reduced input
capacitance for the main switch application in switching
regulators.
Selection criteria for the power MOSFETs include theon”
resistance R
DS(ON)
, input capacitance, breakdown voltage
and maximum output current.
The most important parameter in high voltage applications
is breakdown voltage BV
DSS
. Both the top and bottom
MOSFETs will see full input voltage plus any additional
ringing on the switch node across its drain-to-source dur-
ing its off-time and must be chosen with the appropriate
LTC3703
14
3703fc
applicaTions inForMaTion
breakdown specification. Since many high voltage MOS-
FETs have higher threshold voltages (typically, V
GS(MIN)
≥ 6V), the LTC3703 is designed to be used with a 9V to
15V gate drive supply (DRV
CC
pin).
For maximum efficiency, on-resistance R
DS(ON)
and input
capacitance should be minimized. Low R
DS(ON)
minimizes
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combi-
nation of several components but can be taken from the
typicalgate charge” curve included on most data sheets
(Figure 9).
+
V
DS
V
IN
V
GS
MILLER EFFECT
Q
IN
a b
C
MILLER
= (Q
B
– Q
A
)/V
DS
V
GS
V
+
3703 F09
Figure 9. Gate Charge Characteristic
The curve is generated by forcing a constant input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given V
DS
drain
voltage, but can be adjusted for different V
DS
voltages by
multiplying by the ratio of the application V
DS
to the curve
specified V
DS
values. A way to estimate the C
MILLER
term
is to take the change in gate charge from points a and b
on a manufacturers data sheet and divide by the stated
V
DS
voltage specified. C
MILLER
is the most important se-
lection criteria for determining the transition loss term in
the
top MOSFET but is not directly specified on MOSFET
data sheets. C
RSS
and C
OS
are specified sometimes but
definitions of these parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle =
V
OUT
V
IN
Synchronous Switch Duty Cycle =
V
IN
V
OUT
V
IN
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
P
MAIN
=
V
OUT
V
IN
I
MAX
( )
2
(1+ δ)R
DS(ON)
+
V
IN
2
I
MAX
2
(R
DR
)(C
MILLER
)
1
V
CC
V
TH(IL)
+
1
V
TH(IL)
(f)
P
SYNC
=
V
IN
V
OUT
V
IN
(I
MAX
)
2
(1+ δ)R
DS(0N)
where δ is the temperature dependency of R
DS(ON)
, R
DR
is the effective top driver resistance (approximatelyat
V
GS
= V
MILLER
), V
IN
is the drain potential and the change
in drain potential in the particular application. V
TH(IL)
is
the data sheet specified typical gate threshold voltage
specified in the power MOSFET data sheet at the specified
drain current. C
MILLER
is the calculated capacitance using
the gate charge curve from the MOSFET data sheet and
the technique described above.
Both MOSFETs have I
2
R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V
IN
< 25V,
the high current efficiency generally improves with larger
MOSFETs, while for V
IN
> 25V, the transition losses rapidly
increase to the point that the use of a higher R
DS(ON)
device
with lower C
MILLER
actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short circuit when the synchronous switch is on close
to 100% of the period.
LTC3703
15
3703fc
applicaTions inForMaTion
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs temperature curve, and
typically varies from 0.005/°C to 0.01/°C depending on
the particular MOSFET used.
Multiple MOSFETs can be used in parallel to lower R
DS(ON)
and meet the current and thermal requirements if desired.
The LTC3703 contains large low impedance drivers capable
of driving large gate capacitances without significantly
slowing transition times. In fact, when driving MOSFETs
with very low gate charge, it is sometimes helpful to slow
down the drivers by adding small gate resistors (5Ω or less)
to reduce noise and EMI caused by the fast transitions.
Schottky Diode Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power MOS-
FETs. This prevents the body diode of the bottom MOSFET
from turning on and storing charge during the dead time
and requiring a reverse recovery period that could cost
as much as 1% to 2% in efficiency. A 1A Schottky diode
is generally a good size for 3A to 5A regulators. Larger
diodes result in additional losses due to their larger junc-
tion capacitance. The diode can be omitted
if the efficiency
loss can be tolerated.
Input Capacitor Selection
In
continuous mode, the drain current of the top MOSFET
is approximately a square wave of duty cycle V
OUT
/V
IN
which must be supplied by the input capacitor. To prevent
large input transients, a low ESR input capacitor sized for
the maximum RMS current is given by:
I
CIN(RMS)
I
O(MAX)
V
OUT
V
IN
V
IN
V
OUT
1
1/2
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
=
I
O(MAX)
/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that the ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life. This makes it advisable to further derate the
capacitor or to choose a capacitor rated at a higher tempera-
ture than required. Several capacitors may also be placed in
parallel to meet size or height requirements in the design.
Because tantalum and OS-CON capacitors are not available
in voltages above 30V, for regulators with input supplies
above 30V, choice of input capacitor type is limited to
ceramics or aluminum electrolytics. Ceramic capacitors
have the advantage of very low ESR and can handle high
RMS current, however ceramics with high voltage ratings
(>50V) are not available with more than a few microfarads
of capacitance. Furthermore, ceramics have high voltage
coefficients which means that the capacitance values
decrease even more when used at the rated voltage. X5R
and X7R type ceramics are recommended for their lower
voltage and temperature coefficients. Another consider
-
ation
when using ceramics is their high Q which if not
properly damped, may result in excessive voltage stress
on the power MOSFETs. Aluminum electrolytics have much
higher bulk capacitance, however, they have higher ESR
and lower RMS current ratings.
A good approach is to use a combination of aluminum
electrolytics for bulk capacitance and ceramics for low ESR
and RMS current. If the RMS current cannot be handled
by the aluminum capacitors alone, when used together,
the percentage of RMS current that will be supplied by the
aluminum capacitor is reduced to approximately:
%I
RMS,ALUM
1
1+(8fCR
ESR
)
2
100%
where R
ESR
is the ESR of the aluminum capacitor and C
is the overall capacitance of the ceramic capacitors. Using
an aluminum electrolytic with a ceramic also helps damp
the high Q of the ceramic, minimizing ringing.
Output Capacitor Selection
The selection of C
OUT
is primarily determined by the ESR
required to minimize voltage ripple. The output ripple
(V
OUT
) is approximately equal to:
V
OUT
I
L
ESR+
1
8fC
OUT

LTC3703IGN#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 100V Step-Down DC/DC Controller
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New from this manufacturer.
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