10
IRU3037/IRU3037A & (PbF)
www.irf.com
6) Place second pole at the ESR zero.
FP2 = FESR
Check if R8 >
If R8 is too small, increase R7 and start from step 2.
7) Place second zero around the resonant frequency.
FZ2 = FLC
8) Use equation (1) to calculate R5.
These design rules will give a crossover frequency ap-
proximately one-tenth of the switching frequency. The
higher the band width, the potentially faster the load tran-
sient speed. The gain margin will be large enough to
provide high DC-regulation accuracy (typically -5dB to -
12dB). The phase margin should be greater than 45) for
overall stability.
IC Quiescent Power Dissipation
Power dissipation for IC controller is a function of ap-
plied voltage, gate driver loads and switching frequency.
The IC's maximum power dissipation occurs when the
IC operating with single 12V supply voltage (Vcc=12V
and Vc≅24V) at 400KHz switching frequency and maxi-
mum gate loads.
Figures 9 and 10 show voltage vs. current, when the
gate drivers loaded with 470pF, 1150pF and 1540pF ca-
pacitors. The IC's power dissipation results to an exces-
sive temperature rise. This should be considered when
using IRU3037A for such application.
Layout Consideration
The layout is very important when designing high fre-
quency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
Start to place the power components, make all the con-
nection in the top layer with wide, copper filled areas.
The inductor, output capacitor and the MOSFET should
be close to each other as possible. This helps to reduce
the EMI radiated by the power traces due to the high
switching currents through them. Place input capacitor
directly to the drain of the high-side MOSFET, to reduce
the ESR replace the single input capacitor with two par-
allel units. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC. In multilayer PCB use
one layer as power ground plane and have a control cir-
cuit ground (analog ground), to which all signals are ref-
erenced. The goal is to localize the high current path to
a separate loop that does not interfere with the more
sensitive analog control function. These two grounds
must be connected together on the PC board layout at a
single point.
Figure 8 shows a suggested layout for the critical com-
ponents, based on the schematic on page 14.
Figure 8 - Suggested layout.
(Topside shown only)
1
gm
R8 =
1
2π × C10 × FP2
R6 = - R8
1
2π × C10 × FZ2
R5 = × R6
VREF
VOUT - VREF
C
5
D
1
D
2
IRU3037
1
2
3
45
6
7
8
1
2
3
4
5678
L1
L2
U1
Q1
R4
C4
C9
C8
C3
R5
R6
C1
Vin
C2A, B C7A, B
Analog Gnd
PGnd PGnd
Vout
PGnd
D
3
Single Point
Analog Gnd
Connect to
Power Ground plane
Analog Gnd
PGnd
