AD8051/AD8052/AD8054
Rev. J | Page 19 of 24
ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG
APPLICATIONS
Figure 50 is a schematic showing the AD8051 used as a driver
for an AD9201, a 10-bit, 20 MSPS, dual analog-to-digital
converter. This converter is designed to convert I and Q signals in
communications systems. In this application, only the I channel
is being driven. The I channel is enabled by applying a logic
high to SELECT (Pin 13).
The AD8051 is running from a dual supply and is configured
for a gain of +2. The input signal is terminated in 50  and the
output is 2 V p-p, which is the maximum input range of the
AD9201. The 22  series resistor limits the maximum current
that flows and helps to lower the distortion of the ADC.
The AD9201 has differential inputs for each channel. These are
designated the A and B inputs. The B inputs of each channel are
connected to VREF (Pin 22), which supplies a positive reference
of 2.5 V. Each of the B inputs has a small low-pass filter that also
helps to reduce distortion.
The output of the op amp is ac-coupled into INA-I (Pin 16) via
two parallel capacitors to provide good high frequency and low
frequency coupling. The 1 k resistor references the signal to
VREF that is applied to INB-I. Thus, INA-I swings both positive
and negative with respect to the bias voltage applied to INB-I.
With the sampling clock running at 20 MSPS, the analog-to-
digital output was analyzed with a digital analyzer. Two input
frequencies were used, 1 MHz and 9.5 MHz, which is just short
of the Nyquist frequency. These signals were well filtered to
minimize any harmonics.
Figure 48 shows the FFT response of the ADC for the case of a
1 MHz analog input. The SFDR is 71.66 dB, and the analog-to-
digital is producing 8.8 ENOB (effective number of bits). When
the analog frequency was raised to 9.5 MHz, the SFDR was
reduced to −60.18 dB and the ADC operated with 8.46 ENOBs
as shown in Figure 49. The inclusion of the AD8051 in the
circuit did not worsen the distortion performance of the AD9201.
PART# 0
FCLK
FUND
VIN
THD
SNR
SINAD
ENOB
SFDR
2ND
3RD
4TH
5TH
6TH
7TH
8TH
9TH
FFTSIZE 8192
20.0MHz
998.5kHz
–0.51dB
–68.13
54.97
54.76
8.80
71.66
–74.53
–76.06
–76.35
–79.05
–80.36
–75.08
–88.12
–77.87
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
AMPLITUDE (dB)
FREQUENCY (MHz)
0 12 34567 8910
FUND
2ND
5TH
6TH
7TH
8TH
9TH
4TH3RD
01062-049
Figure 48. FFT Plot for AD8051 Driving the AD9201 at 1 MHz
PART#
0
FCLK
FUND
VIN
THD
SNR
SINAD
ENOB
SFDR
2ND
3RD
4TH
5TH
6TH
7TH
8TH
9TH
FFTSIZE 8192
20.0MHz
9.5MHz
–0.44dB
–57.08
54.65
52.69
8.46
60.18
–60.18
–60.23
–82.01
–78.83
–81.28
–77.28
–84.54
–92.78
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
AMPLITUDE (dB)
FREQUENCY (MHz)
0 1234567 8910
FUND
2ND
5TH
6TH
7TH
8TH
4TH
3RD
01062-050
Figure 49. FFT Plot for AD8051 Driving the AD9201 at 9.5 MHz
AD8051
+5V
VREF
AVDD
SELECT
INA-I
10pF
CLOCK
SLEEP
D9
D1
D2
D3
D4
D5
D6
D7
D0
DVDD
AVSS
REFSENSE
AD9201
DVSS
CHIP–SELECT
INB-I
REFT-I
REFB-I
REFB -Q
REFT -Q
INB-Q
INA-Q
D8
DATA OUT
10pF
–5V
10pF
10pF
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0.1µF 10µF
+5V
+V
DD
10µF0.1µF 0.1µF
0.1µF
10µF
0.1µF
10µF
0.1µF
10µF0.1µF 0.1µF
0.1µF
+5V
22
22
22
22
22
1k
1k
0.33µF
0.01µF
1k
10µF0.1µF
10µF0.1µF
50
3
2
7
4
6
01062-048
Figure 50. The AD8051 Driving an AD9201, a 10-Bit, 20 MSPS Analog-to-Digital Converter
AD8051/AD8052/AD8054
Rev. J | Page 20 of 24
SYNC STRIPPER
Synchronizing pulses are sometimes carried on video signals so
as not to require a separate channel to carry the synchronizing
information. However, for some functions, such as analog-to-
digital conversion, it is not desirable to have the sync pulses on
the video signal. These pulses reduce the dynamic range of the
video signal and do not provide any useful information for such
a function.
A sync stripper removes the synchronizing pulses from a video
signal while passing all the useful video information. Figure 51
shows a practical single-supply circuit that uses only a single
AD8051. It is capable of directly driving a reverse terminated
video line.
AD8051
0.1µF
10µF
+
100
TO A/D
3V OR 5V
V
BLANK
GROUND
0.4V
IDEO WITH SYNC
GROUND
V
IDEO WITHOUT SYNC
R2
1k
R1
1k
V
IN
3
2
7
4
6
0.8V
(OR 2 × V
BLANK
)
0
1062-051
Figure 51. Sync Stripper
The video signal plus sync is applied to the noninverting input
with the proper termination. The amplifier gain is set to 2 via
the two 1 kΩ resistors in the feedback circuit. A bias voltage
must be applied to R1 so that the input signal has the sync
pulses stripped at the proper level.
The blanking level of the input video pulse is the desired place to
remove the sync information. This level is multiplied by 2 by the
amplifier. This level must be at ground at the output for the sync
stripping action to take place. Since the gain of the amplifier from
the input of R1 to the output is −1, a voltage equal to 2 × V
BLANK
must be applied to make the blanking level come out at ground.
SINGLE-SUPPLY COMPOSITE VIDEO LINE DRIVER
Many composite video signals have their blanking level at
ground and have video information that is both positive and
negative. Such signals require dual-supply amplifiers to pass
them. However, by ac level shifting, a single-supply amplifier
can be used to pass these signals. The following complications
can arise from such techniques.
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capacity than their (bounded)
peak-to-peak amplitude after they are ac-coupled. As a worst
case, the dynamic signal swing will approach twice the peak-to-
peak value. The two conditions that define the maximum
dynamic swing requirements are a signal that is mostly low but
goes high with a duty cycle that is a small fraction of a percent,
and the other extreme defined by the opposite condition.
The worst case of composite video is not quite this demanding.
One bounding condition is a signal that is mostly black for an
entire frame but has a white (full amplitude) minimum width
spike at least once in a frame.
The other extreme is for a full white video signal. The blanking
intervals and sync tips of such a signal have negative-going
excursions in compliance with the composite video specifications.
The combination of horizontal and vertical blanking intervals
limit such a signal to being at the highest (white) level for a
maximum of about 75% of the time.
As a result of the duty cycles between the two extremes
previously presented, a 1 V p-p composite video signal that is
multiplied by a gain of 2 requires about 3.2 V p-p of dynamic
voltage swing at the output for an op amp to pass a composite
video signal of arbitrarily varying duty cycle without distortion.
Some circuits use a sync tip clamp to hold the sync tips at a
relatively constant level to lower the amount of dynamic signal
swing required. However, these circuits can have artifacts, such
as sync tip compression, unless they are driven by a source with
a very low output impedance. The AD8051/AD8052/AD8054
have adequate signal swing when running on a single 5 V
supply to handle an ac-coupled composite video signal.
The input to the circuit in Figure 52 is a standard composite
(1 V p-p) video signal that has the blanking level at ground. The
input network level shifts the video signal by means of ac coupling.
The noninverting input of the op amp is biased to half of the
supply voltage.
The feedback circuit provides unity gain for the dc-biasing of
the input and provides a gain of 2 for any signals that are in the
video bandwidth. The output is ac-coupled and terminated to
drive the line.
The capacitor values were selected for providing minimum tilt
or field time distortion of the video signal. These values would
be required for video that is considered to be studio or broadcast
quality. However, if a lower consumer grade of video, sometimes
referred to as consumer video, is all that is desired, the values
and the cost of the capacitors can be reduced by as much as a
factor of five with minimum visible degradation in the picture.
AD8051
5V
+
10µF
4.99k
220µF
+
1000µF
0.1µF
10k
+
47µF
4.99k
0.1µF
10µF
+
COMPOSITE
VIDEO
IN
3
2
7
4
6
R
G
1k
R
F
1k
R
T
75
R
L
75
V
OUT
R
BT
75
0
1062-052
Figure 52. Single-Supply Composite Video Line Driver
AD8051/AD8052/AD8054
Rev. J | Page 21 of 24
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AB
060606-A
14
8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
45°
Figure 53. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
PIN 1
1.60 BSC
2.80 BSC
1.90
BSC
0.95 BSC
5
123
4
0.22
0.08
10°
0.50
0.30
0.15 MAX
SEATING
PLANE
1.45 MAX
1.30
1.15
0.90
2.90 BSC
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178-A A
Figure 54. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters

AD8051ARTZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers SGL RR
Lifecycle:
New from this manufacturer.
Delivery:
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