9DB801CGLF Datasheet 9DB801CGLFT, 9DB801CGLF, 9DB801CFLF | P10-P12

IDT

/ICS

Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11

ICS9DB801C

Eight Output Differential Buffer for PCI Express (50-200MHz)

Vdiff Vp-p Vcm R1 R2 R3 R4 Note

0.45v 0.22v 1.08 33 150 100 100

0.58 0.28 0.6 33 78.7 137 100

0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible

0.60 0.3 1.2 33 174 140 100 Standard LVDS

R1a = R1b = R1

R2a = R2b = R2

Alternative Termination for LVDS and other Common Differential Signals (figure 3)

HCSL Output Buffer

L1'

R1b

L2'

R1a

L4'

R2a R2b

Down Device

REF_CLK Input

Figure 3

L3'

R3 R4

Component Value Note

R5a, R5b 8.2K 5%

R6a, R6b 1K 5%

Cc 0.1 µF

Vcm 0.350 volts

Cable Connected AC Coupled Application (figure 4)

PCIe Device

REF_CLK Input

Figure 4

R5a

L4'

3.3 Volts

R5b

R6a R6b

IDT

/ICS

Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11

ICS9DB801C

Eight Output Differential Buffer for PCI Express (50-200MHz)

General SMBus serial interface information for the ICS9DB801C

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address DC

(h)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will

acknowledge

• Controller (host) sends the data byte count = X

• ICS clock will

acknowledge

• Controller (host) starts sending

Byte N through

Byte N + X -1

• ICS clock will

acknowledge

each byte

one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address DC

(h)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte

location = N

• ICS clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address DD

(h)

• ICS clock will

acknowledge

• ICS clock will send the data byte count = X

• ICS clock sends

Byte N + X -1

• ICS clock sends

Byte 0 through byte X (if X

(h)

was written to byte 8)

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

ICS (Slave/Receiver)

ACK

PstoP bit

X Byte

Index Block Write Operation

Slave Address DC

(h)

Beginning Byte = N

WRite

starT bit

Controller (Host)

Byte N + X - 1

Data Byte Count = X

Beginning Byte N

T starT bit

WR WRite

RT Repeat starT

RD ReaD

Beginning Byte N

Byte N + X - 1

N Not acknowledge

PstoP bit

Slave Address DD

(h)

Index Block Read Operation

Slave Address DC

(h)

Beginning Byte = N

ACK

Data Byte Count = X

ACK

ICS (Slave/Receiver)

Controller (Host)

X Byte

ACK

IDT

/ICS

Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11

ICS9DB801C

Eight Output Differential Buffer for PCI Express (50-200MHz)

SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)

Pin # Name Control Function T

e0 1PWD

Bit

PD_Mode PD# drive mode RW driven Hi-Z 0

Bit

STOP_Mode SRC_Stop# drive mode RW driven Hi-Z 0

Bit

Reserved Reserved RW X

Bit

Reserved Reserved RW X

Bit

Reserved Reserved RW X

Bit 2

PLL_BW# Select PLL BW RW High BW Low BW 1

Bit 1

BYPASS# BYPASS#/PLL RW fan-out ZDB 1

Bit 0

SRC_DIV# SRC Divide by 2 Select RW x/2 1x 1

SMBus Table: Output Control Register

Pin # Name Control Function T

e0 1PWD

Bit

DIF_7 Output Control RW Disable Enable 1

Bit

DIF_6 Output Control RW Disable Enable 1

Bit

DIF_5 Output Control RW Disable Enable 1

Bit

DIF_4 Output Control RW Disable Enable 1

Bit

DIF_3 Output Control RW Disable Enable 1

Bit 2

DIF_2 Output Control RW Disable Enable 1

Bit 1

DIF_1 Output Control RW Disable Enable 1

Bit 0

DIF_0 Output Control RW Disable Enable 1

SMBus Table: Output Control Register

Pin # Name Control Function T

e0 1PWD

Bit

DIF_7 Output Control RW Free-run Stoppable 0

Bit

DIF_6 Output Control RW Free-run Stoppable 0

Bit

DIF_5 Output Control RW Free-run Stoppable 0

Bit

DIF_4 Output Control RW Free-run Stoppable 0

Bit

DIF_3 Output Control RW Free-run Stoppable 0

Bit 2

DIF_2 Output Control RW Free-run Stoppable 0

Bit 1

DIF_1 Output Control RW Free-run Stoppable 0

Bit 0

DIF_0 Output Control RW Free-run Stoppable 0

SMBus Table: Output Control Register

Pin # Name Control Function T

e0 1PWD

Bit

RW X

Bit

RW X

Bit

RW X

Bit

RW X

Bit

RW X

Bit 2

RW X

Bit 1

RW X

Bit 0

RW X

Reserved

Reserved Reserved

12,13

8,9

te 3

Reserved Reserved

34,33

30,29

20,21

16,17

8,9

te 2

42,41

38,37

30,29

20,21

16,17

12,13

te 0

- Reserved

Reserved

te 1

42,41

38,37

34,33

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

9DB801CGLF

Mfr. #:

Buy 9DB801CGLF

Manufacturer:

IDT

Description:

Clock Buffer 8 OUTPUT PCIE GEN1 BUFFER

Lifecycle:

New from this manufacturer.

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9DB801CGLF

9DB801CGLF

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