IDT
TM
/ICS
TM
Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
7
Symbol Parameter Min Max Units
VDD_A 3.3V Core Supply Voltage 4.6 V
VDD_In 3.3V Logic Supply Voltage 4.6 V
V
IL
Input Low Voltage GND-0.5 V
V
IH
Input High Voltage V
DD
+0.5V V
Ts Storage Temperature -65 150
°
C
Tambient Ambient Operating Temp 0 70 °C
Tcase Case Temperature 115 °C
ESD prot
Input ESD protection
human body model
2000 V
Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage V
IH
3.3 V +/-5% 2 V
DD
+ 0.3 V
Input Low Voltage V
IL
3.3 V +/-5% GND
- 0.3 0.8 V
Input High Current I
IH
V
IN
= V
DD
-5 5 uA
I
IL1
V
IN
= 0 V; Inputs with no pull-
up resistors
-5 uA
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200 uA
I
DD3.3PLL
175 200 mA
I
DD3.3B
y
Pass
160 175 mA
all diff pairs driven 50 70 mA
all differential pairs tri-stated 1 4 mA
Input Frequency F
iPLL
PLL Mode 50 200 MHz
Input Frequency F
iBypass
Bypass Mode (Revision
B/REV ID = 1H)
0 333.33 MHz
Input Frequency F
iBypass
Bypass Mode (Revision
C/REV ID = 2H)
0400MHz
Pin Inductance
1
L
pin
7nH1
C
IN
Logic Inputs 1.5 4 pF 1
C
OUT
Output pin capacitance 4 pF 1
PLL Bandwidth when
PLL_BW=0
2.4 3 3.4 MHz 1
PLL Bandwidth when
PLL_BW=1
0.7 1 1.4 MHz 1
Clk Stabilization
1,2
T
STAB
From V
DD
Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
0.5 1 ms 1,2
Modulation Frequency fMOD Triangular Modulation 30 33 kHz 1
Tdrive_SRC_STOP#
DIF output enable after
SRC_Stop# de-assertion
10 15 ns 1,3
Tdrive_PD#
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall
Fall time of PD# and
SRC_STOP#
5ns1
Trise
Rise time of PD# and
SRC_STOP#
5ns2
1
Guaranteed by design and characterization, not 100% tested in production.
2
See timing diagrams for timing requirements.
I
DD3.3PD
3
Time from deassertion until out
p
uts are >200 mV
Input Capacitance
1
Input Low Current
Powerdown Current
PLL Bandwidth BW
Full Active, C
L
= Full load; Operating Supply Current
IDT
TM
/ICS
TM
Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
8
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T
A
= 0 - 7C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2
Ω
, R
P
=49.9
Ω, Ι
REF
= 475Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output
Im
p
edance
Zo
1
V
O
= V
x
3000
Ω
1
Voltage High VHigh 660 850 1,3
Voltage Low VLow -150 150 1,3
Max Volta
g
e Vovs 1150 1
Min Volta
g
e Vuds -300 1
Crossin
g
Volta
g
e
(
abs
)
Vcross
(
abs
)
250 550 mV 1
Crossing Voltage (var) d-Vcross
Variation of crossing over all
ed
g
es
140 mV 1
Lon
Accurac
pp
m see T
p
eriod min-max values 0
pp
m1,2
Rise Time
t
r
V
OL
= 0.175V, V
OH
= 0.525V
175 700 ps 1
Fall Time
t
f
V
OH
= 0.525V V
OL
= 0.175V
175 700 ps 1
Rise Time Variation
d-t
r
125 ps 1
Fall Time Variation
d-t
f
125 ps 1
Duty Cycle
d
t3
Measurement from differential
wavefrom
45 55 % 1
Skew
t
sk3
V
T
= 50%
50 ps 1
PLL mode,
Measurement from differential
wavefrom
50 ps 1
BYPASS mode as additive
j
itter 50
p
s1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
.
Statistical measurement on single
ended signal using oscilloscope
math function.
mV
Measurement on single ended
signal using absolute value.
mV
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock
complies with CK409/CK410 accuracy requirements
Jitter, Cycle to cycle
t
jcyc-cyc
Electrical Characteristics - Clock Input Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES
Differential Input High Voltage V
IHDIF
Differential inputs
(single-ended measurement)
600 1150 mV 1
Differential Input Low Voltage V
ILDIF
Differential inputs
(single-ended measurement)
V
SS
- 300 300 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA 1
Input Duty Cycle d
tin
Measurement from differential
wavefrom
45 55 % 1
Input SRC Jitter - Cycle to
Cycle
SRCJ
C2CIn
Differential Measurement 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through Vswing centered around differential zero
IDT
TM
/ICS
TM
Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
9
Common Recommendations for Differential Routing Dimension or Value Unit Figure
L1 length, route as non-coupled 50ohm trace 0.5 max inch 1
L2 length, route as non-coupled 50ohm trace 0.2 max inch 1
L3 length, route as non-coupled 50ohm trace 0.2 max inch 1
Rs 33 ohm 1
Rt 49.9 ohm 1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1
L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2
L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2
SRC Reference Clock
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt
PCI Express
Down Device
REF_CLK Input
Figure 1: Down Device Routing
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt
PCI Express
Add-in Board
REF_CLK Input
Figure 2: PCI Express Connector Routing

9DB801CGLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 8 OUTPUT PCIE GEN1 BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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