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Document History Page
Document Title: SL28506-2 Clock Generator for Intel
®
Eaglelake Chipset
DOC #: SP-AP-0021 (Rev AB)
REV. ECR# Issue Date
Orig. of
Change Description of Change
1.0 7/12/07 JMA New data sheet
1.1 7/18/07 JMA Merged TSSOP and SSOP into one datasheet
1.2 7/19/07 JMA Changed part number ordering information
1.3 12/15/07 BSHEN
Changed part number ordering information to SL28506BZC
Changed Revision ID to 0001
1.4 6/18/08 JMA 1. Removed “Priliminary Confidential” wording
2. Changed operating temperature from 0C - 85C to 0C to 70C
3. Added Pb and ROHs compliant note
1.5 10/23/08 JMA 1. Changed operating temperature back to 0-85C
AA 1458 4/7/10 JMA 1. Added new feature for XIN to support also CLKIN input
2. Updated revision and ordering information
3. Updated JEDEC information
4. Updated format to be ISO compliant
5. Merged commercial and industrial temperature
6. Updated TSSOP package drawing
7. Removed SSOP package
AB 1458 5/17/10 JMA 1. Added Bit 0 in Byte 3
2. Updated package ID in Byte 8 to reflect package
3. Updated Feature portion to include exclusion of SRC0 and SRC1 from PCIe
Gen 2 requirements
4. Updated Byte 11 Bit 1 to be a read only bit
5. Added note to specified SRC0 and SRC1 are note PCIe Gen2 compliant.
6. Specified Byte 11 bit 1 is a read only bit.
