DS2760
10
TEMPERATURE MEASUREMENT
The DS2760 uses an integrated temperature sensor to continually measure battery temperature.
Temperature measurements are placed in the Temperature Register in two’s-complement format with a
resolution of 0.125°C over a range of ±127°C. The Temperature Register format is shown in Figure 8.
TEMPERATURE REGISTER FORMAT Figure 8
MSB—Address 18 LSB—Address 19
S 2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
X X X X X
MSb LSb MSb LSb
Units: 0.125°C
PROGRAMMABLE I/O
To use the PIO pin as an output, write the desired output value to the PIO bit in the Special Feature
Register. Writing a 0 to the PIO bit enables the PIO output driver, pulling the PIO pin to VSS. Writing a
1 to the PIO bit disables the output driver, allowing the PIO pin to be pulled high or used as an input. To
sense the value on the PIO pin, read the PIO bit. The DS2760 turns off the PIO output driver and sets the
PIO high when it enters Sleep Mode or when DQ is low for more than 2 seconds, regardless of the state
of the PMOD bit.
POWER SWITCH INPUT
The DS2760 provides a power control function that uses the discharge protection FET to gate battery
power to the system. The
PS
pin, internally pulled to V
DD
through a 1mA current source, is continuously
monitored for a low-impedance connection to VSS. If the DS2760 is in Sleep Mode, the detection of a
low on
PS
causes the device to transition into Active Mode, turning on the discharge FET. If the DS2760
is already in Active Mode, activity on
PS
has no effect other than the mirroring of its logic level in the
PS
bit in the Special Feature Register. The reading of a 0 in the
PS
bit should be immediately followed
by writing a 1 to the
PS
bit to ensure proper operation.
MEMORY
The DS2760 has a 256-byte linear address space with registers for instrumentation, status and control in
the lower 32 bytes, with lockable EEPROM and SRAM memory occupying portions of the remaining
address space. All EEPROM and SRAM memory is general-purpose except addresses 30h, 31h, and 33h,
which should be written with the default values for the Protection Register, Status Register, and Current
Offset Register, respectively. When the MSB of any 2-byte register is read, both the MSB and LSB are
latched and held for the duration of the Read Data command to prevent updates during the read and
ensure synchronization between the two register bytes. For consistent results, always read the MSB and
the LSB of a two-byte register during the same Read Data command sequence.
EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow
the data to be verified by the host system before being copied to EEPROM. All reads and writes to/from
EEPROM memory actually access the shadow RAM. In unlocked EEPROM blocks, the Write Data
command updates shadow RAM. In locked EEPROM blocks, the Write Data command is ignored. The
Copy Data command copies the contents of shadow RAM to EEPROM in an unlocked block of
EEPROM but has no effect on locked blocks. The Recall Data command copies the contents of a block of
EEPROM to shadow RAM regardless of whether the block is locked or not.
