DS2760BE+025 Datasheet DS2760BE+025, DS2760BE+, DS2760AE+ | P4-P6

DS2760

DETAILED PIN DESCRIPTION Table 1

SYMBOL TSSOP* FLIP

CHIP*

DESCRIPTION

1 C1 Charge Protection Control Output. Controls an external p-channel

high-side charge protection FET.

3 B2 Discharge Protection Control Output. Controls an external p-channel

high-side discharge protection FET.

DQ 7 B4 Data Input/Out. 1-Wire data line. Open-drain output driver. Connect

this pin to the DATA terminal of the battery pack. Pin has an internal

1mA pull-down for sensing disconnection.

PIO

14 E2 Programmable I/O Pin. Used to control and monitor user-defined

external circuitry. Open drain to VSS.

PLS 2 B1 Battery Pack Positive Terminal Input. The device monitors the state of

the battery pack’s positive terminal through this pin in order to detect

events such as the attachment of a charger or the removal of a short

circuit. Additionally, a charge path to recover a deeply depleted cell is

provided from PLS to VDD.

10 E4 Power Switch Sense Input. The device wakes up from Sleep Mode

when it senses the closure of a switch to VSS on this pin. Pin has an

internal 1mA pull-up to V

VIN 16 D1 Voltage Sense Input. The voltage of the Li+ cell is monitored via this

input pin. This pin has a weak pullup to V

15 E1 Power Supply Input. Connect to the positive terminal of the Li+ cell

through a decoupling network.

VSS

11,12,13 F3 Device Ground. Connect directly to the negative terminal of the Li+ cell.

For the external sense resistor configuration, connect the sense resistor

between VSS and SNS.

SNS 4,5,6 A3 Sense Resistor Connection. Connect to the negative terminal of the

battery pack. In the internal sense resistor configuration, the sense resistor

is connected between VSS and SNS.

IS1 9 D4 Current Sense Input. This pin is internally connected to VSS through a

4.7kW resistor. Connect a 0.1m F capacitor between IS1 and IS2 to

complete a low-pass input filter.

IS2 8 C4 Current Sense Input. This pin is internally connected to SNS through a

4.7kW resistor.

SNS

Probe

N/A C2

Do Not Connect.

VSS

Probe

N/A D2

Do Not Connect.

* Mechanical drawing for the 16-pin TSSOP and DS2760 flip-chip package can be found at:

http://pdfserv.maxim-ic.com/arpdf/Packages/16tssop.pdf

http://pdfserv.maxim-ic.com/arpdf/Packages/chips/2760x.pdf

DS2760

APPLICATION EXAMPLE Figure 2

1 – R

SENS

is present for external sense resistor configurations only

2 – R

SENSINT

is present for internal sense resistor configurations only

SNS

DS2760

VSS

IS2 IS1

4.7kW

voltage

sense

SENSINT

(2)

PACK+

PACK-

DAT

150W

150

150W

DS2760

104

PLS

SNS

IS2

VIN

PIO

VSS

IS1

102

104

BAT+

BAT-

SENS

(1)

4.7kW

DS2760

POWER MODES

The DS2760 has two power modes: Active and Sleep. While in Active Mode, the DS2760 continually

measures current, voltage and temperature to provide data to the host system and to support current

accumulation and Li+ safety monitoring. In Sleep Mode, the DS2760 ceases these activities. The

DS2760 enters Sleep Mode when any of the following conditions occurs:

§ the PMOD bit in the Status Register has been set to 1 and the DQ line is low for longer than

2 seconds (pack disconnection)

§ the voltage on VIN drops below undervoltage threshold V

for t

UVD

(cell depletion)

§ the pack is disabled through the issuance of a SWAP command (SWEN bit =1)

The DS2760 returns to Active Mode when any of the following occurs:

§ the PMOD bit has been set to 1 and the SWEN bit is set to 0 and the DQ line is pulled high

(pack connection)

§ the

pin is pulled low (power switch)

§ the voltage on PLS becomes greater than the voltage on VIN (charger connection) with the SWEN bit

set to 0

§ the pack is enabled through the issuance of a SWAP command (SWEN bit =1)

The DS2760 defaults to Sleep Mode when power is first applied.

LI+ PROTECTION CIRCUITRY

During Active Mode, the DS2760 constantly monitors cell voltage and current to protect the battery from

overcharge (overvoltage), overdischarge (undervoltage) and excessive charge and discharge currents

(overcurrent, short circuit). Conditions and DS2760 responses are described in the sections below and

summarized in Table 2 and Figure 3.

LI+ PROTECTION CONDITIONS AND DS2760 RESPONSES Table 2

Activation Condition

Name

Threshold Delay Response

Release

Threshold

Overvoltage VIN

> V

OVD CC

high

VIN

< V

Undervoltage VIN

< V

UVD CC

high,

Sleep Mode

PLS

> V

(1)

(charger connected)

Overcurrent, Charge V

> V

(2)

OCD CC

high

PLS

< V

– V

(3)

Overcurrent, Discharge V

< -V

(2)

OCD DC

high

PLS

> V

– V

(4)

Short Circuit V

SNS

> V

SCD DC

high

PLS

> V

– V

(4)

= V

IS1

– V

IS2

. Logic high = V

PLS

for

and V

for

All voltages are with respect to VSS. I

SNS

references current delivered from pin SNS.

(1) If V

<2.2V, release is delayed until the recovery charge current (I

) passed from PLS to V

charges the battery and allows V

to exceed 2.2V.

(2) for the internal sense resistor configuration, the overcurrent thresholds are expressed in terms of

current: I

SNS

> I

for charge direction and I

SNS

< -I

for discharge direction

(3) with test current I

TST

current flowing from PLS to VSS (pull-down on PLS)

(4) with test current I

TST

current flowing from V

to PLS (pull-up on PLS)

Overvoltage. If the voltage of the cell exceeds overvoltage threshold V

for a period longer than

overvoltage delay t

OVD

, the DS2760 shuts off the external charge FET and sets the OV flag in the

Protection Register. When the cell voltage falls below charge enable threshold V

, the DS2760 turns the

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

DS2760BE+025

Mfr. #:

Buy DS2760BE+025

Manufacturer:

Maxim Integrated

Description:

Battery Management

Lifecycle:

New from this manufacturer.

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DS2760BE+025

DS2760BE+025

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