NCL30088
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19
As illustrated in Figure 59, the V
S
pin provides the
sinusoidal reference necessary for shaping the input current.
The obtained current reference is further modulated so that
when averaged over a half−line period, it is equal to the
output current reference (V
REFX
). This averaging process is
made by an internal Operational Trans−conductance
Amplifier (OTA) and the capacitor connected to the COMP
pin (C1 of Figure 59). Typical COMP capacitance is 1 mF
and should not be less than 470 nF to ensure stability. The
COMP ripple does not affect the power factor performance
as the circuit digitally eliminates it when generating the
current setpoint.
If the V
S
pin properly conveys the sinusoidal shape, power
factor will be close to unity and the Total Harmonic
Distortion (THD) will be low. In any case, the output current
will be well regulated following the equation below:
I
out
+
V
REFX
2N
PS
R
sense
(eq. 1)
Where:
N
PS
is the secondary to primary transformer turns
N
PS
= N
S
/N
P
. N
PS
is 1 in the case of non−isolated
buck−boost or SEPIC converter.
R
sense
is the current sense resistor (see Figure 1).
V
REFX
is the output current internal reference.
V
REFX
= V
REF
(250 mV in A and B versions and
200 mV in C and D versions, typically) at full load.
The output current reference (V
REFX
) is V
REF
unless the
temperature is high enough to activate the thermal fold−back
(see “protections” section).
If a major fault is detected, the circuit enters the
latched−off or auto−recovery mode and the COMP pin is
grounded (except in an UVLO condition). This ensures a
clean start−up when the circuit resumes operation.
Start−up Sequence
Generally an LED lamp is expected to emit light in < 1 sec
and typically within 300 ms. The start−up phase consists of
the time to charge the V
CC
capacitor, begin switching and
the time to charge the output capacitor until sufficient
current flows into the LED string. To speed−up this phase,
the following defines the start−up sequence:
The COMP pin is grounded when the circuit is off. The
average COMP voltage needs to exceed the V
S
pin
peak value to have the LED current properly regulated
(whatever the current target is). To speed−up the COMP
capacitance charge and shorten the start−up phase, an
internal 80−mA current source adds to the OTA sourced
current (60 mA max typically) to charge up the COMP
capacitance. The 80−mA current source remains on until
the OTA starts to sink current as a result of the COMP
pin voltage sufficient rise. At that moment, the COMP
pin being near its steady−state value, it is only driven
by the OTA.
If V
CC
drops below the V
CC(off)
threshold because the
circuit fails to start−up properly on the first attempt, a
new try takes place as soon as V
CC
is recharged to
V
CC(on)
. The COMP voltage is not reset at that
moment. Instead, the new attempt starts with the
COMP level obtained at the end of the previous
operating phase.
If the load is shorted, the circuit will operate in hiccup
mode with V
CC
oscillating between V
CC(off)
and
V
CC(on)
until the AUX_SCP protection trips
(AUX_SCP is triggered if the ZCD pin voltage does
not exceed 1 V within a 90−ms operation period of time
thus indicating a short to ground of the ZCD pin or an
excessive load preventing the output voltage from
rising). The NCL30088A and NCL30088C latch off in
this case. With the B and D versions, the AUX_SCP
protection forces the 4−s auto−recovery delay to reduce
the operation duty−ratio. Figure 60 illustrates a start−up
sequence with the output shorted to ground, in this
second case.
NCL30088
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20
CC(on)
V
CC(off)
V
()
4
recovery
ts^
()
‧‧‧
1
t
2
t
3
t
()
123
90
OVLD
OVLD
AUX_SCPtrips
as t t t
tms
+
^
1
t
2
t
3
t
()
4
recovery
ts^
()
‧‧‧
CC
V
DRV
time
time
Figure 60. Start−up Sequence in a Load Short−circuit Situation (auto−recovery versions)
t +=
Zero Crossing Detection Block
The ZCD pin detects when the drain−source voltage of the
power MOSFET reaches a valley by crossing below the
55−mV internal threshold. At startup or in case of extremely
damped free oscillations, the ZCD comparator may not be
able to detect the valleys. To avoid such a situation, the
NCL30088 features a time−out circuit that generates pulses
if the voltage on ZCD pin stays below the 55−mV threshold
for 6.5 ms. The time−out also acts as a substitute clock for the
valley detection and simulates a missing valley in case the
free oscillations are too damped.
Figure 61. Zero Current Detection Block
NCL30088
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21
If the ZCD pin or the auxiliary winding happen to be
shorted, the time−out function would normally make the
controller keep switching and hence lead to improper LED
current value. The “AUX_SCP” protection prevents such a
stressful operation: a secondary timer starts counting that is
only reset when the ZCD voltage exceeds the V
ZCD(short)
threshold (1 V typically). If this timer reaches 90 ms (no
ZCD voltage pulse having exceeded V
ZCD(short)
for this time
period), the controller detects a fault and stops operation for
4 seconds (B and D versions) or latches off (A and C
versions).
The “clock” shown in Figure 61 is used by the “valley
selection frequency foldback” circuitry of the block diagram
(Figure 3), to generate the next DRV pulse (if no fault
prevents it):
Immediately when the clock occurs in QR mode at low
line or valley 2 at high line (full load)
After the appropriate number of “clock” pulses in
thermal foldback mode
For an optimal operation, the maximum ZCD level
should be maintained below 5 V to stay safely below the
built in clamping voltage of the pin.
Line Range Detection
As sketched in Figure 62, this circuit detects the low−line
range if the V
S
pin remains below the V
LL
threshold (2.3 V
typical) for more than the 25−ms blanking time. High−line
is detected as soon as the V
S
pin voltage exceeds V
HL
(2.4 V
typical). These levels roughly correspond to 184−V rms and
192−V rms line voltages if the external resistors divider
applied to the V
S
pin is designed to provide a 1−V peak value
at 80 V rms.
Figure 62. Line Range Detection
In the low-line range, conduction losses are generally
dominant. Adding a dead-time would further increase these
losses. Hence, only a short dead-time is necessary to reach
the MOSFET valley. In high-line conditions, switching
losses generally are the most critical. It is thus efficient to
skip one valley to lower the switching frequency. Hence,
under normal operation, the NCL30088 optimizes the
efficiency over the line range by turning on the MOSFET at
the first valley in low-line conditions and at the second
valley in the high-line case. This is illustrated by Figure 63
that sketches the MOSFET Drain-source voltage in both
cases. In the event that thermal foldback is activated,
additional valleys can be skipped as the power is reduced.
Figure 63. Full−load Operation − Quasi−resonant Mode in low line (left), turn on at valley 2 when in high line (right)
Line Feedforward
As illustrated by Figure 64, the input voltage is sensed by
the V
S
pin and converted into a current. By adding an
external resistor in series between the sense resistor and the
CS pin, a voltage offset proportional to the input voltage is
added to the CS signal for the MOSFET on−time.

NCL30088BDR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
LED Lighting Drivers LED LIGHTING CONTRLR T
Lifecycle:
New from this manufacturer.
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