LTC3203/LTC3203-1
LTC3203B/LTC3203B-1
12
32031fa
APPLICATIO S I FOR ATIO
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For the example given, a 5V output setting with ±4% output
tolerance and maximum load current of 500mA, a resistor
ratio of:
R
R
MODE
MODE
1
2
4>
at the MODE pin allows the chip to switch modes while
maintaining regulation.
V
IN
, V
OUT
Capacitor Selection
The style and value of capacitors used with the
LTC3203/LTC3203-1/LTC3203B/LTC3203B-1 determine
several important parameters such as regulator control
loop stability, output ripple, charge pump strength and
minimum start-up time.
To reduce noise and ripple, it is recommended that low
equivalent series resistance (ESR) multilayer ceramic chip
capacitors (MLCCs) be used for both C
IN
and C
OUT
. Tanta-
lum and aluminum capacitors are not recommended be-
cause of their high ESR.
In 1.5x mode, the value of C
OUT
directly controls the
amount of output ripple for a given load current. Increasing
the size of C
OUT
will reduce the output ripple at the expense
of higher minimum turn-on time and higher start-up cur-
rent. The peak-to-peak output ripple for 1.5x mode is given
by the expression:
V
I
fC
RIPPLE P P
OUT
OSC OUT
()−
=
•3
where f
OSC
is the LTC3203/LTC3203-1/LTC3203B/
LTC3203B-1’s oscillator frequency (typically 0.9MHz) and
C
OUT
is the output charge storage capacitor.
In 2x mode, the output ripple is very low due to the out-of-
phase operation of the two flying capacitors. V
OUT
remains
almost flat when either of the flying capacitors is connected
to V
OUT
.
Both the type and value of the output capacitor can signifi-
cantly affect the stability of the LTC3203/LTC3203-1/
LTC3203B/LTC3203B-1. As shown in the Block Diagram,
the LTC3203/LTC3203-1/LTC3203B/LTC3203B-1 use a
control loop to adjust the strength of the charge pump to
match the current required at the output. The error signal
of this loop is stored directly on the output charge storage
capacitor. The charge storage capacitor also serves to
form the dominant pole for the control loop. To prevent
ringing or instability, it is important for the output capaci-
tor to maintain at least 4.7µF of capacitance over all
conditions. Note that the actual capacitance of ceramic
capacitors usually drops when biased with DC voltage.
Different capacitor types drop to different extents. Make
sure that the selected ceramic capacitors have enough
capacitance when biased with the required DC voltage.
Likewise, excessive ESR on the output capacitor will tend
to degrade the loop stability of the LTC3203/LTC3203-1/
LTC3203B/LTC3203B-1. The closed-loop output resis-
tance of the LTC3203/LTC3203-1/LTC3203B/LTC3203B-
1 are designed to be 0.27Ω (at 1.5x mode). For a 100mA
load current change, the output voltage will change by
about 27mV. If the output capacitor has 0.27Ω or more of
ESR, the closed-loop frequency response will cease to
roll-off in a simple one-pole fashion and poor load tran-
sient response or instability could result. Multilayer ce-
ramic chip capacitors typically have exceptional ESR per-
formance and, combined with a good board layout, should
yield very good stability and load transient performance.
As the value of C
OUT
controls the amount of output ripple,
the value of C
IN
controls the amount of ripple present at the
input pin (V
IN
). The input current to the LTC3203/
LTC3203-1/LTC3203B/LTC3203B-1 will be relatively con-
stant while the charge pump is on either the input charging
phase or the output charging phase but will drop to zero
during the clock non-overlap times. Since the non-overlap
time is small (~40ns) these missing “notches” will result
in only a small perturbation on the input power supply line.
Note that a higher ESR capacitor such as tantalum
will have higher input noise by the amount of the input
current change times the ESR. Therefore ceramic
capacitors are again recommended for their exceptional
ESR performance. Further input noise reduction can be
achieved by powering the LTC3203/LTC3203-1/LTC3203B/
LTC3203B-1 through a very small series inductor as
shown in Figure 5.
