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MAX11645EUA+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
16 ______________________________________________________________________________________
Data Byte (Read Cycle)
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing a
START condition followed by seven address bits and a
read bit (R/W = 1). If the address byte is successfully
received, the MAX11644/MAX11645 (slave) issues an
acknowledge. The master then reads from the slave.
The result is transmitted in 2 bytes; first 4 bits of the first
byte are high, then MSB through LSB are consecutively
clocked out. After the master has received the byte(s), it
can issue an acknowledge if it wants to continue read-
ing or a not-acknowledge if it no longer wishes to read.
If the MAX11644/MAX11645 receive a not-acknowl-
edge, they release SDA, allowing the master to generate
a STOP or a repeated START condition. See the
Clock
Modes
and
Scan Mode
sections for detailed information
on how data is obtained and converted.
Clock Modes
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the set-
up byte’s CLK bit determines the clock mode (Table 1).
At power-up, the MAX11644/MAX11645 are defaulted
to internal clock mode (CLK = 0).
Internal Clock
When configured for internal clock mode (CLK = 0), the
MAX11644/MAX11645 use their internal oscillator as
the conversion clock. In internal clock mode, the
MAX11644/MAX11645 begin tracking the analog input
after a valid address on the eighth rising edge of the
clock. On the falling edge of the ninth clock, the analog
signal is acquired and the conversion begins. While
converting the analog input signal, the MAX11644/
MAX11645 hold SCL low (clock stretching). After the
conversion completes, the results are stored in internal
memory. If the scan mode is set for multiple conver-
sions, they all happen in succession with each addi-
tional result stored in memory. The MAX11644/
MAX11645 contain two 12-bit blocks of memory. Once
all conversions are complete, the MAX11644/
MAX11645 release SCL, allowing it to be pulled high.
The master can now clock the results out of the memo-
ry in the same order the scan conversion has been
done at a clock rate of up to 1.7MHz. SCL is stretched
for a maximum of 8.3μs per channel (see Figure 10).
The device memory contains all of the conversion
results when the MAX11644/MAX11645 release SCL.
The converted results are read back in a first-in-first-out
(FIFO) sequence. The memory contents can be read
continuously. If reading continues past the result stored
in memory, the pointer wraps around and points to the
first result. Note that only the current conversion results
are read from memory. The device must be addressed
with a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during con-
version. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
Figure 10. Internal Clock Mode Read Cycles
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
______________________________________________________________________________________ 17
External Clock
When configured for external clock mode (CLK = 1),
the MAX11644/MAX11645 use the SCL as the conver-
sion clock. In external clock mode, the MAX11644/
MAX11645 begin tracking the analog input on the ninth
rising clock edge of a valid slave address byte. Two
SCL clock cycles later, the analog signal is acquired
and the conversion begins. Unlike the internal clock
mode, converted data is available immediately after the
first four empty high bits. The device continuously con-
verts input channels dictated by the scan mode until
given a not-acknowledge. There is no need to read-
dress the device with a read command to obtain new
conversion results (see Figure 11).
The conversion must complete in 1ms, or droop on the
track-and-hold capacitor degrades conversion results.
Use internal clock mode if the SCL clock period
exceeds 60μs.
The MAX11644/MAX11645 must operate in external
clock mode for conversion rates from 40ksps to
94.4ksps. Below 40ksps, internal clock mode is recom-
mended due to much smaller power consumption.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. The scanned results are written to memo-
ry in the same order as the conversion. Read the results
from memory in the order they were converted. Each
result needs a 2-byte transmission; the first byte begins
with 4 empty bits, during which SDA is left high. Each
byte has to be acknowledged by the master or the mem-
ory transmission is terminated. It is not possible to read
the memory independently of conversion.
Figure 11. External Clock Mode Read Cycle
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS0.
0 1 Converts the input selected by CS0 eight times (see Tables 3 and 4).*
1 0 Reserved. Do not use.
1 1 Converts the input selected by CS0.*
*
When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11, and converting occurs
perpetually until not-acknowledge occurs.
Table 5. Scanning Configuration
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
18 ______________________________________________________________________________________
Applications Information
Power-On Reset
The configuration and setup registers (Tables 1 and 2)
default to a single-ended, unipolar, single-channel con-
version on AIN0 using the internal clock with V
DD
as the
reference. The memory contents are unknown after
power-up.
Automatic Shutdown
Automatic shutdown occurs between conversions when
the MAX11644/MAX11645 are idle. All analog circuits
participate in automatic shutdown except the internal
reference due to its prohibitively long wake-up time.
When operating in external clock mode, a STOP, not-
acknowledge, or repeated START condition must be
issued to place the devices in idle mode and benefit
from automatic shutdown. A STOP condition is not nec-
essary in internal clock mode to benefit from automatic
shutdown because power-down occurs once all con-
version results are written to memory (Figure 10). When
using an external reference or V
DD
as a reference, all
analog circuitry is inactive in shutdown and supply cur-
rent is less than 0.5μA. The digital conversion results
obtained in internal clock mode are maintained in mem-
ory during shutdown and are available for access
through the serial interface at any time prior to a STOP
or a repeated START condition.
When idle, the MAX11644/MAX11645 continuously wait
for a START condition followed by their slave address
(see the
Slave Address
section). Upon reading a valid
address byte, the MAX11644/MAX11645 power up. The
internal reference requires 10ms to wake up, so when
using the internal reference it should be powered up
10ms prior to conversion or powered continuously.
Wake-up is invisible when using an external reference
or V
DD
as the reference.
Automatic shutdown results in dramatic power savings,
particularly at slow conversion rates and with internal
clock. For example, at a conversion rate of 10ksps, the
average supply current for the MAX11645 is 60μA (typ)
and drops to 6μA (typ) at 1ksps. At 0.1ksps the aver-
age supply current is just 1μA, or a minuscule 3μW of
power consumption. See Average Supply Current vs.
Conversion Rate (External Clock) in the
Typical
Operating Characteristics
section).
Reference Voltage
SEL[2:0] of the setup byte (Table 1) control the refer-
ence configuration (Table 6).
Internal Reference
The internal reference is 4.096V for the MAX11644 and
2.048V for the MAX11645. When REF is configured to
be an internal reference output (SEL[2:1] = 11), decou-
ple REF to GND with a 0.1μF capacitor and a 2kΩ
series resistor (see the
Typical Operating Circuit
). Once
powered up, the reference always remains on until
reconfigured. The internal reference requires 10ms to
wake up and is accessed using SEL0 (Table 6). When
in shutdown, the internal reference output is in a high-
impedance state. The reference should not be used to
supply current for external circuitry. The internal refer-
ence does not require an external bypass capacitor
and works best when left unconnected (SEL1 = 0).
External Reference
The external reference can range from 1V to V
DD
. For
maximum conversion accuracy, the reference must be
able to deliver up to 40μA and have an output imped-
ance of 500kΩ or less. If the reference has a higher
output impedance or is noisy, bypass it to GND as
close as possible to REF with a 0.1μF capacitor.
SEL2 SEL1 SEL0
REFERENCE
VOLTAGE
REF
INTERNAL REFERENCE
STATE
00X V
DD
Not connected Always off
0 1 X External reference Reference input Always off
1 0 0 Internal reference Not connected* Always off
1 0 1 Internal reference Not connected* Always on
1 1 0 Internal reference Reference output Always off
1 1 1 Internal reference Reference output Always on
Table 6. Reference Voltage and REF Format
X = Don’t care.
*Preferred configuration for internal reference.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

MAX11645EUA+T

Mfr. #:
Buy MAX11645EUA+T
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 2Ch 94.4ksps 3.6V Precision ADC
Lifecycle:
New from this manufacturer.
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