TIMING CHARACTERISTICS (Figure 1) (continued)
(V
DD
= 2.7V to 3.6V (MAX11645), V
DD
= 4.5V to 5.5V (MAX11644), V
REF
= 2.048V (MAX11645), V
REF
= 4.096V (MAX11644),
f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C, see Tables 1–5 for programming
notation.) (Note 1)
Note 1: All WLP devices are 100% production tested at T
A
= +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2: For DC accuracy, the MAX11644 is tested at V
DD
= 5V and the MAX11645 is tested at V
DD
= 3V with an external
reference for both ADCs. All devices are configured for unipolar, single-ended inputs.
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4: Offset nulled.
Note 5: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7: The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to V
DD
.
Note 8: When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a
0.1μF capacitor and a 2kΩ series resistor (see the
Typical Operating Circuit
).
Note 9: ADC performance is limited by the converter’s noise floor, typically 300μV
P-P
.
Note 10: Measured for the MAX11645 as:
and for the MAX11644, where N is the number of bits:
Note 11: A master device must provide a data hold time for SDA (referred to V
IL
of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12: The minimum value is specified at T
A
= +25°C.
Note 13: C
B
= total capacitance of one bus line in pF.
Note 14: f
SCL
must meet the minimum clock low time plus the rise/fall times.
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