OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LPC2290FBD144/01,5

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
LPC2290_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 16 November 2006 19 of 41
NXP Semiconductors
LPC2290
16/32-bit ARM microcontroller with external memory interface
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in baud rate generator.
• Standard modem interface signals included on UART1.
6.10.2 UART features available in LPC2290/01 only
• The transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs and hardware (CTS/RTS) flow control on UART1 only.
• Fractional baud rate generator enables standard baud rates such as 115200 to be
achieved with any crystal frequency above 2 MHz.
• Auto-bauding.
• Auto-CTS/RTS flow-control fully implemented in hardware.
6.11 I
2
C-bus serial I/O controller
The I
2
C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C-bus is a multi-master bus, it can be
controlled by more than one bus master connected to it.
The I
2
C-bus implemented in LPC2290 supports bit rate up to 400 kbit/s (Fast I
2
C-bus).
6.11.1 Features
• Compliant with standard I
2
C-bus interface.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I
2
C-bus may be used for test and diagnostic purposes.
6.12 SPI serial I/O controller
The LPC2290 contains two SPIs. The SPI is a full duplex serial interface, designed to be
able to handle multiple masters and slaves connected to a given bus. Only a single master
and a single slave can communicate on the interface during a given data transfer. During a
data transfer the master always sends a byte of data to the slave, and the slave always
sends a byte of data to the master.
LPC2290_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 16 November 2006 20 of 41
NXP Semiconductors
LPC2290
16/32-bit ARM microcontroller with external memory interface
6.12.1 Features
• Compliant with SPI specification.
• Synchronous, serial, full duplex, communication.
• Combined SPI master and slave.
• Maximum data bit rate of one eighth of the input clock rate.
6.13 SSP serial I/O controller (available in LPC2290/01 only)
The LPC2290/01 contains one Serial Synchronous Port controller (SSP). The SSP
controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact
with multiple masters and slaves on the bus. However, only a single master and a single
slave can communicate on the bus during a given data transfer. The SSP supports full
duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. Often only one of these data flows carries
meaningful data.
The SSP and SPI1 share the same pins on LPC2290/01. After a reset, SPI1 is enabled
and SSP is disabled.
6.13.1 Features
• Synchronous Serial Communication.
• 8-frame FIFOs for both transmit and receive.
• Compatible with Motorola SPI, 4-wire TI SSI and National Semiconductor Microwire
buses.
• Master or slave operation.
• Four bits to 16 bits per SPI frame.
6.14 General purpose timers
The TIMER0 and TIMER1 are designed to count cycles of the peripheral clock (PCLK)
and optionally generate interrupts or perform other actions at specified timer values,
based on four match registers. It also includes four capture inputs to trap the timer value
when an input signal transitions, optionally generating an interrupt. Multiple pins can be
selected to perform a single capture or match function, providing an application with ‘or’
and ‘and’, as well as ‘broadcast’ functions among them.
6.14.1 Features
• A 32-bit Timer/Counter with a programmable 32-bit prescaler.
• Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an
interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
LPC2290_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 16 November 2006 21 of 41
NXP Semiconductors
LPC2290
16/32-bit ARM microcontroller with external memory interface
• Four external outputs per timer corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
6.14.2 Timer features available in LPC2290/01 only
• Timers can count cycles of the externally supplied clock providing external event
counting functionality
6.15 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
6.15.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect/incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 32-bit timer with internal pre-scaler.
• Selectable time period from (T
cy(PCLK)
× 256 × 4) to (T
cy(PCLK)
× 2
32
× 4) in multiples of
T
cy(PCLK)
× 4.
6.16 Real-time clock
The Real-Time Clock (RTC) is designed to provide a set of counters to measure time
when normal or idle operating mode is selected. The RTC has been designed to use little
power, making it suitable for battery powered systems where the CPU is not running
continuously (Idle mode).
6.16.1 Features
• Measures the passage of time to maintain a calendar and clock.
• Ultra-low power design to support battery powered systems.
• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day
of Year.
• Programmable Reference Clock Divider allows adjustment of the RTC to match
various crystal frequencies.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41

LPC2290FBD144/01,5

Mfr. #:
Buy LPC2290FBD144/01,5
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 16KR/2CAN/ADC ROMLESS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet