10
IR3621 & (PbF)
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Frequency Synchronization
The IR3621 is capable of accepting an external digital
synchronization signal. Synchronization will be enabled
by the rising edge at an external clock. Per-channel switch-
ing frequency is set by external resistor (Rt). The free
running oscillator frequency is twice the per-channel fre-
quency. During synchronization, Rt is selected such that
the free running frequency is 20% below the sync fre-
quency. Synchronization capability is provided for both 2-
output and 2-phase configurations. When unused, the
Sync pin will remain floating and is noise immune.
Thermal Shutdown
Temperature sensing is provided inside IR3621. The trip
threshold is typically set to 140C. When trip threshold is
exceeded, thermal shutdown turns off both MOSFETs.
Thermal shutdown is not latched and automatic restart is
initiated when the sensed temperature drops to normal
range. There is a 20C hysteresis in the shutdown thresh-
old.
Shutdown
The outputs can be shutdown independently by pulling
the respective soft-start pins below 0.3V. This can be
easily done by using an external small signal transis-
tor. During shutdown both MOSFETs will be turned off.
During this mode the LDO will stay on. Normal opera-
tion will resume by cycling soft start pins.
Operation Frequency Selection
Power Good
The IR3621 provides a power good signal. The power good
signal should be available after both outputs have reached
regulation. This pin needs to be externally pulled high.
High state indicates that outputs are in regulation.
Power good will be low if either one of the output voltages
is 10% below the set value. There is only one power good
for both outputs.
Over-Voltage Protection OVP
Over-voltage is sensed through separate V
OUT sense pins
VSEN1 and VSEN2. A separate OVP circuit is provided for
each output. Upon over-voltage condition of either one of
the outputs, the OVP forces a latched shutdown on both
outputs. In this mode, the upper FET drivers turn off and
the lower FET drivers turn on, thus crowbaring the out-
puts. Reset is performed by recycling Vcc.
Error Amplifier
The IR3621 is a voltage mode controller. The error ampli-
fiers are of transconductance type. In independent mode,
each amplifier closes the loop around its own output volt-
age. In current sharing mode, amplifier 1 becomes the
master which regulates the common output voltage. Am-
plifier 2 performs the current sharing function. Both am-
plifiers are capable of operating with Type III compensa-
tion control scheme.
Figure 10- Switching Frequency versus External Resistor.
The optimum operating frequency range for the IR3621
is 300kHz per phase, theoretically the IR3621 can be
operated at higher switching frequency (e.g. 500kHz).
However the power dissipation for IC, which is function
of applied voltage, gate drivers load and switching fre-
quency, will result in higher junction temperature of de-
vice. It may exceed absolute maximum rating of junc-
tion temperature, figure 18 (page 17) shows case tem-
perature versus switching frequency with different ca-
pacitive loads for TSSOP package.
This should be considered when using IR3621 for such
application. The below equation shows the relationship
between the IC's maximum power dissipation and Junc-
tion temperature:
Where:
Tj: Maximum Operating Junction Temperature
TA: Ambient Temperature
θ
JA = Thermal Impedance of package
The switching frequency is determined by an external
resistor (Rt). The switching frequency is approximately
inversely proportioned to resistance (see Fig 10).
Pd =
ΤJ-ΤA
θJA
Per Channel Switching Frequency vs. RT
0
100
200
300
400
500
600
700
0 10203040506070
RT (kohm)
Switching Frequency (kHz)
IR3621 & (PbF)
11
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APPLICATION INFORMATION
Design Example:
The following example is a typical application for the
IR3621, the schematic is Figure19 on page18.
Output Voltage Programming
Output voltage is programmed by the reference voltage
and an external voltage divider. The Fb1 pin is the invert-
ing input of the error amplifier, which is referenced to the
voltage on the non-inverting pin of error amplifier. For this
application, this pin (V
P2) is connected to the reference
voltage (VREF). The output voltage is defined by using the
following equation:
When an external resistor divider is connected to the
output as shown in Figure 11.
Figure 11 - Typical application of the IR3621 for pro-
gramming the output voltage.
Equation (4) can be rewritten as:
Will result to:
VOUT(2.5V) = 2.5V
VREF = 0.8V
R9= 2.15K, R5= 1K
If the high value feedback resistors are used, the input
bias current of the Fb pin could cause a slight increase
in output voltage. The output voltage can be set more
accurately by using low value, precision resistors.
For a start-up time of 4ms for both output, the soft-start
capacitor will be 0.1µF. Connect two 0.1µFceramic
capacitors from SS1 pin and SS2 pin to GND.
Supply VcH1 and VcH2
To drive the high side MOSFET, it is necessary to sup-
ply a gate voltage at least 4V greater than the bus volt-
age. This is achieved by using a charge pump configu-
ration as shown in Figure 12. This method is simple
and inexpensive. The operation of the circuit is as fol-
lows: when the lower MOSFET is turned on, the ca-
pacitor (C1) charges up to VOUT3, through the diode
(D1). The bus voltage will be added to this voltage when
upper MOSFET turns on in next cycle, and providing
supply voltage (VcH1) through diode (D2). VcH1 is ap-
proximately:
Capacitor in the range of 0.1µF is generally adequate
for most applications. The diode must be a fast recov-
ery device to minimize the amount of charge fed back
from the charge pump capacitor into VOUT3. The diodes
need to be able to block the full power rail voltage, which
is seen when the high side MOSFET is switched on.
For low voltage application, Schottky diodes can be
used to minimize forward drop across the diodes at
start up.
Figure 12 - Charge pump circuit.
R6 = R5 ×
- 1
VOUT
VP
( )
Fb
IR3621
V
OUT
R
5
R
6
V
REF
V
P2
VCH1 VOUT3 + VBUS - (VD1 + VD2)
V
IN = 12V
VOUT(2.5V) = 2.5V @ 10A
VOUT(1.8V) = 1.8V @ 10A
VOUT = Output voltage ripple 3% of VOUT
FS = 400kHz
L2
IR3621
D1
C1
VcH1
HDrv
Regulator
Q1
Q2
V
OUT3
C2
V
BUS
D2
C3
Css 28×tSTART (µF) ---(5)
Where tSTART is the desired start-up time (ms)
VOUT = VP2 × 1 +
---(4)
R6
R5
VP2 = VREF = 0.8V
( )
VOUT(1.8V) = 1.8V
VREF = 0.8
R7= 1.24K, R8 = 1K
Soft-Start Programming
The soft-start timing can be programmed by selecting
the soft-start capacitance value. The start-up time of
the converter can be calculated by using:
12
IR3621 & (PbF)
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For higher efficiency, low ESR capacitors are recom-
mended.
Choose two Poscap from Sanyo 16TPB47M (16V, 47µF,
70m) with a maximum allowable ripple current of 1.4A
for inputs of each channel.
Inductor Selection
The inductor is selected based on operating frequency,
transient performance and allowable output voltage ripple.
Low inductor values result in faster response to step
load (high i/t) and smaller size but will cause larger
output ripple due to increased inductor ripple current. As
a rule of thumb, select an inductor that produces a ripple
current of 10-40% of full load DC.
For the buck converter, the inductor value for desired
operating ripple current can be determined using the fol-
lowing relation:
VIN - VOUT = L× ; t = D× ; D =
1
fS
VOUT
VIN
i
t
L = (VIN - VOUT)× ---(7)
VOUT
VIN×∆i×fS
Where:
VIN = Maximum Input Voltage
VOUT = Output Voltage
i = Inductor Ripple Current
fS = Switching Frequency
t = Turn On Time
D = Duty Cycle
Where:
VO = Output Voltage Ripple
i = Inductor Ripple Current
VO = 3% of VO will result to ESR(2.5V) =16.6mand
ESR(1.8V) =16m
ESR ---(8)
VO
IO
The Sanyo TPC series, Poscap capacitor is a good choice.
The 6TPC330M, 330µF, 6.3V has an ESR 40m. Se-
lecting three of these capacitors in parallel for 2.5V out-
put, results to an ESR of 13.3m which achieves our
low ESR goal. And selecting three of these capacitors in
parallel for 1.8V output, results in an ESR of 13.3m
which achieves our low ESR goal.
The capacitors value must be high enough to absorb the
inductor's ripple current.
Power MOSFET Selection
The IR3621 uses four N-Channel MOSFETs. The selec-
tion criteria to meet power transfer requirements is based
on maximum drain-source voltage (VDSS), gate-source
drive voltage (VGS), maximum output current, On-resis-
tance RDS(ON) and thermal management.
The both control and synchronous MOSFETs must have
a maximum operating voltage (VDSS) that exceeds the
maximum input voltage (VIN).
Input Capacitor Selection
The 180
0
out of phase will reduce the RMS value of the
ripple current seen by input capacitors. This reduces
numbers of input capacitors. The input capacitors must
be selected that can handle both the maximum ripple
RMS at highest ambient temperature as well as the
maximum input voltage. The RMS value of current ripple
for duty cycles under 50% is expressed by:
For i(2.5V) = 45%(IO(2.5V) ), then the output inductor will
be:
L4 = 1.1µH
For i(1.8V) = 35%(IO(1.8V) ), then the output inductor will
be:
L3 = 1.1µH
Panasonic provides a range of inductors in different val-
ues and low profile for large currents.
Output Capacitor Selection
The criteria to select the output capacitor is normally
based on the value of the Effective Series Resistance
(ESR). In general, the output capacitor must have low
enough ESR to meet output ripple and load transient
requirements, yet have high enough ESR to satisfy sta-
bility requirements. The ESR of the output capacitor is
calculated by the following relationship:
I
RMS
= (I
1
2
D
1
(1-D
1
)+I
2
2
D
2
(1-D
2
)-2I
1
I
2
D
1
D
2
) --- (6)
Where:
I
RMS
is the RMS value of the input capacitor current
D
1
and D
2
are the duty cycle for each output
I
1
and I
2
are the current for each output
For this application the I
RMS
=4.8A
(ESL, Equivalent Series Inductance is neglected)
Choose ETQP6F1R1BFA (1.1µH, 16A, 2.2m) both for
L3 and L4.
For 2-phase application, equation (7) can be used for
calculating the inductors value. In such case the induc-
tor ripple current is usually chosen to be between 10-
40% of maximum phase current.

IR3621FTRPBF

Mfr. #:
Manufacturer:
Infineon / IR
Description:
Switching Controllers
Lifecycle:
New from this manufacturer.
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