IR3621 & (PbF)
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Choose IRF7821 for control MOSFETs and IRF8113 for
synchronous MOSFETs. These devices provide low on-
resistance in a compact SOIC 8-Pin package.
The MOSFETs have the following data:
The total conduction losses for each output will be:
The switching loss is more difficult to calculate, even
though the switching transition is well understood. The
reason is the effect of the parasitic components and
switching times during the switching procedures such
as turn-on / turnoff delays and rise and fall times. The
control MOSFET contributes to the majority of the switch-
ing losses in a synchronous Buck converter. The syn-
chronous MOSFET turns on under zero voltage condi-
tions, therefore, the switching losses for synchronous
MOSFET can be neglected. With a linear approxima-
tion, the total switching loss can be expressed as:
These values are taken under a certain condition test.
For more details please refer to the IRF7821 data sheet.
By using equation (9), we can calculate the total switch-
ing losses.
Programming the Over-Current Limit
The over-current threshold can be set by connecting a
resistor (RSET) from drain of low side MOSFET to the
OCSet pin. The resistor can be calculated by using equa-
tion (3).
The RDS(on) has a positive temperature coefficient and it
should be considered for the worse case operation.
PCON(TOTAL, 2.5V) = PCON(UPPER) + PCON(LOWER)
PCON(TOTAL, 2.5V) = 1.0W
PSW(TOTAL,2.5V) = 0.18W
PSW(TOTAL,1.8V) = 0.18W
IRF7821
VDSS = 30V
RDS(on) = 9m
Where:
VDS(OFF) = Drain to Source Voltage at off time
tr = Rise Time
tf = Fall Time
T = Switching Period
I
LOAD = Load Current
P
SW = ILOAD ---(9)
×
VDS(OFF)
2
tr + tf
T
×
IRF7821
tr = 2.7ns
tf = 7.3ns
RDS(on) = 6mΩ×1.5 = 9m
ISET IO(LIM) = 10A×1.5 = 15A
(50% over nominal output current)
This results to:
RSET = R1=R6=6.75K
V
DS
V
GS
10%
90%
t
d
(ON)
t
d
(OFF)
t
r
t
f
Figure 13 - Switching time waveforms.
From IRF7821 data sheet we obtain:
2
2
PCOND(Upper Switch) = ILOAD×RDS(on)×D×ϑ
PCOND(Lower Switch) = ILOAD×RDS(on)×(1 - D)×ϑ
ϑ = RDS(on) Temperature Dependency
The gate drive requirement is almost the same for both
MOSFETs. Logic-level transistors can be used and cau-
tion should be taken with devices at very low V
GS to pre-
vent undesired turn-on of the complementary MOSFET,
which results in a shoot-through.
The total power dissipation for MOSFETs includes con-
duction and switching losses. For the Buck converter,
the average inductor current is equal to the DC
load current. The conduction loss is defined as:
The R
DS(ON) temperature dependency should be consid-
ered for the worst case operation. This is typically given
in the MOSFET data sheet. Ensure that the conduction
losses and switching losses do not exceed the package
ratings or violate the overall thermal budget.
PCON(TOTAL, 1.8V) = PCON(UPPER) + PCON(LOWER)
PCON(TOTAL, 1.8V) = 1.0W
IRF8113
VDSS = 30V
RDS(on) = 6m
This resistor must be placed close to the IC, place a
small ceramic capacitor from this pin to ground for noise
rejection purposes.
14
IR3621 & (PbF)
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The ESR zero of the output capacitor is expressed as
follows:
Figure 15 - Compensation network without local
feedback and its asymptotic gain plot.
The transfer function (Ve / V
OUT) is given by:
The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a gain
and zero, expressed by:
|H(s)| is the gain at zero cross frequency.
First select the desired zero-crossover frequency (F
O1
):
V
OUT
Vp=V
REF
R
5
R
9
R
4
C
9
Ve
E/A
F
Z
H(s) dB
Frequency
Gain(dB)
Fb
Comp
C
POLE
FESR = ---(10A)
1
2π×ESR×Co
H(s) = gm× × ---(11)
( )
R5
R9 + R5
1 + sR4C9
sC9
FZ = ---(13)
1
2π×R4×C9
|H(s=j×2π×FO)| = gm× ×R4 ---(12)
R5
R9+R5
Feedback Compensation
The IR3621 is a voltage mode controller; the control loop
is a single voltage feedback path including error ampli-
fier and error comparator. To achieve fast transient re-
sponse and accurate output regulation, a compensation
circuit is necessary. The goal of the compensation net-
work is to provide a closed loop transfer function with
the highest 0dB crossing frequency and adequate phase
margin (greater than 45).
The output LC filter introduces a double pole, –40dB/
decade gain slope above its corner resonant frequency,
and a total phase lag of 180 (see Figure 14). The Reso-
nant frequency of the LC filter is expressed as follows:
Where: Lo is the output inductor
For 2-phase application, the effective output
inductance should be used
Co is the total output capacitor
Figure 14 shows gain and phase of the LC filter. Since
we already have 180 phase shift just from the output
filter, the system risks being unstable.
FLC = ---(10)
1
2π× LO×CO
Gain
F
LC
0dB
Phase
0
F
LC
-180
Frequency
Frequency
-40dB/decade
Figure14 - Gain and phase of LC filter
The IR3621’s error amplifier is a differential-input transcon-
ductance amplifier. The output is available for DC gain
control or AC phase compensation.
The E/A can be compensated with or without the use of
local feedback. When operated without local feedback,
the transconductance properties of the E/A become evi-
dent and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC circuit
from Comp pin to ground as shown in Figure 15.
Note that this method requires the output capacitor to
have enough ESR to satisfy stability requirements. In
general, the output capacitor’s ESR generates a zero
typically at 5kHz to 50kHz which is essential for an ac-
ceptable phase margin.
F
O1
> FESR and F
O1
(1/5 ~ 1/10)×fS
IR3621 & (PbF)
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Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
F
O1
= Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
R5 and R9 = Resistor Dividers for Output Voltage
Programming
g
m = Error Amplifier Transconductance
This results to R4=4.8K
Choose R4=5K
To cancel one of the LC filter poles, place the zero be-
fore the LC filter resonant frequency pole:
Using equations (13) and (15) to calculate C9, we get:
Same calcuation For V1.8V will result to: R3 = 4.2K and
C8 = 10nF
One more capacitor is sometimes added in parallel with
C9 and R4. This introduces one more pole which is mainly
used to suppress the switching noise. The additional
pole is given by:
The pole sets to one half of switching frequency which
results in the capacitor CPOLE:
C9 8.3nF; Choose C9 =8.2nF
FLC = 5.06kHz
R5 = 1K
R9 = 2.14K
gm = 1400µmho
For V2.5V:
VIN = 12V
VOSC = 1.25V
F
O1
= 40KHz
FESR = 13.3kHz
R4 = × × × ---(14)
F
O1
×FESR
FLC
2
VOSC
VIN
R5 + R9
R5
1
gm
For:
Lo = 1.1µH
Co = 990µF
FZ 75%FLC
FZ 0.75×
1
2π LO × CO
---(15)
FZ = 3.61kHz
R4 = 5K
FP =
2π×R4×
1
C9×CPOLE
C9 + CPOLE
CPOLE =
for FP <<
fS
2
1
π×R4×fS
π×R4×fS -
1
1
C9
For a general solution for unconditional stability for ce-
ramic output capacitor with very low ESR or any type of
output capacitors, in a wide range of ESR values we
should implement local feedback with a compensation
network. The typically used compensation network for a
voltage-mode controller is shown in Figure 16.
Figure 16- Compensation network with local
feedback and its asymptotic gain plot.
In such configuration, the transfer function is given by:
The error amplifier gain is independent of the transcon-
ductance under the following condition:
By replacing ZIN and Zf according to Figure 16, the trans-
former function can be expressed as:
As known, transconductance amplifier has high imped-
ance (current source) output, therefore, consider should
be taken when loading the E/A output. It may exceed its
source/sink output current capability, so that the ampli-
fier will not be able to swing its output voltage over the
necessary range.
The compensation network has three poles and two ze-
ros and they are expressed as follows:
1 - gmZf
1 + gmZIN
Ve
VOUT
=
gmZf >> 1 and gmZIN >>1 ---(16)
H(s) =
1+sR7
×(1+sR8C10)
(1+sR7C11)×[1+sC10(R6+R8)]
×
[ ( )]
1
sR6(C12+C11)
C12C11
C12+C11
V
OUT
V
P2
=V
REF
R
5
R
6
R
8
C
10
C
12
C
11
R
7
Ve
F
Z
1
F
Z
2
F
P
2
F
P
3
E/A
Z
f
Z
IN
Frequency
Gain(dB)
H(s) dB
Fb
Comp

IR3621FTRPBF

Mfr. #:
Manufacturer:
Infineon / IR
Description:
Switching Controllers
Lifecycle:
New from this manufacturer.
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