AD7874
REV. C
–9–
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD7874, THD is defined as
THD = 20log
V
2
2
+V
3
2
+V
4
2
+V
5
2
+V
6
2
V
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
and V
6
are the rms amplitudes of the second through the
sixth harmonic. The THD is also derived from the FFT plot of
the ADC output spectrum.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3 . . ., etc. Intermodulation terms are those for
which neither m or n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb) while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Using the CCIF standard where two input frequencies near the
top end of the input bandwidth are used, the second and third
order terms are of different significance. The second order terms
are usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third order
terms are specified separately. The calculation of the intermodu-
lation distortion is as per the THD specification where it is the
ratio of the rms sum of the individual distortion products to the
rms amplitude of the fundamental expressed in dBs. In this case,
the input consists of two, equal amplitude, low distortion sine
waves. Figure 10 shows a typical IMD plot for the AD7874.
Figure 10. AD7874 IMD Plot
Peak Harmonic or Spurious Noise
Harmonic or Spurious Noise is defined as the ratio of the rms
value of the next largest component in the ADC output spec-
trum (up to fs/2 and excluding dc) to the rms value of the fun-
damental. Normally, the value of this specification will be
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor the peak
will be a noise peak.
AC Linearity Plot
When a sine wave of specified frequency is applied to the V
IN
in-
put of the AD7874 and several million samples are taken, a his-
togram showing the frequency of occurrence of each of the 4096
ADC codes can be generated. From this histogram data it is
possible to generate an ac integral linearity plot as shown in Fig-
ure 11. This shows very good integral linearity performance
from the AD7874 at an input frequency of 10 kHz. The absence
of large spikes in the plot shows good differential linearity. Sim-
plified versions of the formulae used are outlined below.
INL(i) =
(V(i)V(o))4096
V( fs)V(o)
i
where INL(i) is the integral linearity at code i. V(fs) and V(o) are
the estimated full-scale and offset transitions, and V(i) is the es-
timated transition for the i
th
code.
V(i), the estimated code transition point is derived as follows:
V(i) =−ACos
π⋅cum(i)
[]
N
where A is the peak signal amplitude, N is the number of histo-
gram samples
and cum(i) =
n=o
i
V(n)occurrences
Figure 11. AD7874 AC INL Plot
AD7874
REV. C
–10–
MICROPROCESSOR INTERFACING
The AD7874 high speed bus timing allows direct interfacing to
DSP processors as well as modern 16-bit microprocessors.
Suitable microprocessor interfaces are shown in Figures 12
through 16.
AD7874–ADSP-2100 Interface
Figure 12 shows an interface between the AD7874 and the
ADSP-2100. Conversion is initiated using a timer which allows
very accurate control of the sampling instant on all four chan-
nels. The AD7874
INT line provides an interrupt to the ADSP-
2100 when conversion is completed on all four channels. The
four conversion results can then be read from the AD7874 using
four successive reads to the same memory address. The follow-
ing instruction reads one of the four results (this instruction is
repeated four times to read all four results in sequence):
MR0 = DM(ADC)
where MR0 is the ADSP-2100 MR0 register and
ADC is the AD7874 address.
TIMER
DMA0
DMA13
DMD15
DMD0
DMS
EN
ADDR
DECODE
ADDRESS BUS
ADSP-2100
(ADSP-2101/
ADSP-2102)
* ADDITIONAL PINS OMITTED FOR CLARITY
DATA BUS
CONVST
CS
DB11
DB0
RD
INT
AD7874*
IRQn
DMRD (RD)
Figure 12. AD7874–ADSP-2100 Interface
AD7874–ADSP-2101/ADSP-2102 Interface
The interface outlined in Figure 12 also forms the basis for an
interface between the AD7874 and the ADSP-2101/ADSP-2102.
The READ line of the ADSP-2101/ADSP-2102 is labeled
RD.
In this interface, the
RD pulse width of the processor can be
programmed using the Data Memory Wait State Control Regis-
ter. The instruction used to read one of the four results is as
outlined for the ADSP-2100.
AD7874–TMS32010 Interface
An interface between the AD7874 and the TMS32010 is shown
in Figure 13. Once again the conversion is initiated using an ex-
ternal timer and the TMS32010 is interrupted when all four
conversions have been completed. The following instruction is
used to read the conversion results from the AD7874:
IN D,ADC
where D is Data Memory address and
ADC is the AD7874 address.
PA0
PA2
D15
D0
MEN
EN
ADDR
DECODE
ADDRESS BUS
TIMER
DATA BUS
CONVST
CS
DB11
DB0
RD
INT
AD7874*
TMS32010
*ADDITIONAL PINS OMITTED FOR CLARITY
INT
DEN
Figure 13. AD7874–TMS32010 Interface
AD7874–TMS320C25 Interface
Figure 14 shows an interface between the AD7874 and the
TMS320C25. As with the two previous interfaces, conversion is
initiated with a timer and the processor is interrupted when the
conversion sequence is completed. The TMS320C25 does not
have a separate
RD output to drive the AD7874 RD input di-
rectly. This has to be generated from the processor STRB and
R/
W outputs with the addition of some logic gates. The RD sig-
nal is OR-gated with the MSC signal to provide the one WAIT
state required in the read cycle for correct interface timing.
Conversion results are read from the AD7874 using the follow-
ing instruction:
IN D,ADC
where D is Data Memory address and
ADC is the AD7874 address.
A0
A15
D15
D0
IS
EN
ADDR
DECODE
ADDRESS BUS
TIMER
DATA BUS
CONVST
CS
DB11
DB0
RD
INT
AD7874*
TMS320C25
*ADDITIONAL PINS OMITTED FOR CLARITY
INTn
R/W
STRB
MSC
READY
Figure 14. AD7874–TMS320C25 Interface
AD7874
REV. C
–11–
Some applications may require that the conversion is initiated
by the microprocessor rather than an external timer. One option
is to decode the AD7874
CONVST from the address bus so
that a write operation starts a conversion. Data is read at the
end of the conversion sequence as before. Figure 16 shows an
example of initiating conversion using this method. Note that
for all interfaces, a read operation should not be attempted dur-
ing conversion.
AD7874–MC68000 Interface
An interface between the AD7874 and the MC68000 is shown
in Figure 15. As before, conversion is initiated using an external
timer. The AD7874
INT line can be used to interrupt the pro-
cessor or, alternatively, software delays can ensure that conver-
sion has been completed before a read to the AD7874 is
attempted. Because of the nature of its interrupts, the 68000
requires additional logic (not shown in Figure 15) to allow it to
be interrupted correctly. For further information on 68000 in-
terrupts, consult the 68000 users manual.
The MC68000
AS and R/W outputs are used to generate a
separate
RD input signal for the AD7874. CS is used to drive
the 68000
DTACK input to allow the processor to execute a
normal read operation to the AD7874. The conversion results
are read using the following 68000 instruction:
MOVE.W ADC,D0
where D0 is the 68000 D0 register and
ADC is the AD7874 address.
A0
A15
D15
D0
ADDR
DECODE
ADDRESS BUS
DATA BUS
CONVST
CS
DB11
DB0
RD
AD7874*
MC68000
*ADDITIONAL PINS OMITTED FOR CLARITY
R/W
AS
EN
DTACK
TIMER
Figure 15. AD7874–MC68000 Interface
AD7874–8086 Interface
Figure 16 shows an interface between the AD7874 and the 8086
microprocessor. Unlike the previous interface examples, the
microprocessor initiates conversion. This is achieved by gating
the 8086
WR signal with a decoded address output (different to
the AD7874
CS address). The AD7874 INT line is used to in-
terrupt the microprocessor when the conversion sequence is
completed. Data is read from the AD7874 using the following
instruction:
MOV AX,ADC
where AX is the 8086 accumulator and
ADC is the AD7874 address.
ALE
AD15
AD0
ADDR
DECODE
ADDRESS BUS
ADDRESS/DATA BUS
CONVST
CS
DB11
DB0
RD
AD7874*
8086
*ADDITIONAL PINS OMITTED FOR CLARITY
WR
RD
LATCH
Figure 16. AD7874–8086 Interface

AD7874BRZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Data Acquisition System IC 12-Bit
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union