AD7874BRZ Datasheet AD7874BRZ, AD7874ANZ, AD7874BNZ | P7-P9

AD7874

REV. C

–6–

CONVERTER DETAILS

The AD7874 is a complete 12-bit, 4-channel data acquisition

system. It is comprised of a 12-bit successive approximation

ADC, four high speed track/hold circuits, a four-channel analog

multiplexer and a 3 V Zener reference. The ADC uses a succes-

sive approximation technique and is based on a fast-settling,

voltage switching DAC, a high speed comparator, a fast CMOS

SAR and high speed logic.

Conversion is initiated on the rising edge of

CONVST. All four

input track/holds go from track to hold on this edge. Conversion

is first performed on the Channel 1 input voltage, then Channel

2 is converted and so on. The four results are stored in on-chip

registers. When all four conversions have been completed,

INT

goes low indicating that data can be read from these locations.

The conversion sequence takes either 78 or 79 rising clock edges

depending on the synchronization of

CONVST with CLK. In-

ternal delays and reset times bring the total conversion time

from

CONVST going high to INT going low to 32.5 µs maxi-

mum for a 2.5 MHz external clock. The AD7874 uses an im-

plicit addressing scheme whereby four successive reads to the

same memory location access the four data words sequentially.

The first read accesses Channel 1 data, the second read accesses

Channel 2 data and so on. Individual data registers cannot be

accessed independently.

INTERNAL REFERENCE

The AD7874 has an on-chip temperature compensated buried

Zener reference which is factory trimmed to 3 V ± 10 mV (see

Figure 3). The reference voltage is provided at the REF OUT

pin. This reference can be used to provide both the reference

voltage for the ADC and the bipolar bias circuitry. This is

achieved by connecting REF OUT to REF IN.

TEMPERATURE

COMPENSATION

AD7874

REF OUT

Figure 3. AD7874 Internal Reference

The reference can also be used as a reference for other compo-

nents and is capable of providing up to 500 µA to an external

load. In systems using several AD7874s, using the REF OUT of

one device to provide the REF IN for the other devices ensures

good full-scale tracking between all the AD7874s. Because the

AD7874 REF IN is buffered, each AD7874 presents a high im-

pedance to the reference so one AD7874 REF OUT can drive

several AD7874 REF INs.

The maximum recommended capacitance on REF OUT for

normal operation is 50 pF. If the reference is required for other

system uses, it should be decoupled to AGND with a 200 Ω re-

sistor in series with a parallel combination of a 10 µF tantalum

capacitor and a 0.1 µF ceramic capacitor.

EXTERNAL REFERENCE

In some applications, the user may require a system reference or

some other external reference to drive the AD7874 reference in-

put. Figure 4 shows how the AD586 5 V reference can be used

to provide the 3 V reference required by the AD7874 REF IN.

GND

OUT

AGND

10kΩ

15kΩ

1kΩ

IN1

TO INTERNAL

COMPARATOR

TRACK/HOLD 1

TO ADC

REFERENCE

CIRCUITRY

7R*

2.1R* 3R*

AD7874**

REF

15V

AD586

*R = 3.6kΩ TYP

**ADDITIONAL PINS OMITTED FOR CLARITY

Figure 4. AD586 Driving AD7874 REF IN

TRACK-AND-HOLD AMPLIFIER

The track-and-hold amplifier on each analog input of the

AD7874 allows the ADC to accurately convert an input sine

wave of 20 V p-p amplitude to 12-bit accuracy. The input band-

width of the track/hold amplifier is greater than the Nyquist rate

of the ADC even when the ADC is operated at its maximum

throughput rate. The small signal 3 dB cutoff frequency occurs

typically at 500 kHz.

The four track/hold amplifiers sample their respective input

channels simultaneously. The aperture delay of the track/hold

circuits is small and, more importantly, is well matched across

the four track/holds on one device and also well matched from

device to device. This allows the relative phase information be-

tween different input channels to be accurately preserved. It also

allows multiple AD7874s to sample more than four channels

simultaneously.

The operation of the track/hold amplifiers is essentially transpar-

ent to the user. Once conversion is initiated, the four channels

are automatically converted and there is no need to select which

channel is to be digitized.

ANALOG INPUT

The analog input of Channel 1 of the AD7874 is as shown in

Figure 4. The analog input range is ±10 V into an input resis-

tance of typically 30 kΩ. The designed code transitions occur

midway between successive integer LSB values (i.e., 1/2 LSB,

3/2 LSBs, 5/2 LSBs, . . . FS – 3/2 LSBs). The output code is

2s complement binary with 1 LSB = FS/4096 = 20 V/4096 =

4.88 mV. The ideal input/output transfer function is shown in

Figure 5.

AD7874

REV. C

–7–

–

FS=20V

1LSB =

4096

OUTPUT

CODE

INPUT VOLTAGE

011...111

011...110

000...010

000...001

000...000

111...111

111...110

100...001

100...000

1LSB–

Figure 5. Input/Output Transfer Function

OFFSET AND FULL-SCALE ADJUSTMENT

In most Digital Signal Processing (DSP) applications, offset and

full-scale errors have little or no effect on system performance.

Offset error can always be eliminated in the analog domain by

ac coupling. Full-scale error effect is linear and does not cause

problems as long as the input signal is within the full dynamic

range of the ADC. Invariably, some applications will require

that the input signal span the full analog input dynamic range.

In such applications, offset and full-scale error will have to be

adjusted to zero.

Figure 6 shows a circuit which can be used to adjust the offset

and full-scale errors on the AD7874 (Channel 1 is shown for ex-

ample purposes only). Where adjustment is required, offset er-

ror must be adjusted before full-scale error. This is achieved by

trimming the offset of the op amp driving the analog input of

the AD7874 while the input voltage is a 1/2 LSB below analog

ground. The trim procedure is as follows: apply a voltage of

–2.44 mV (–1/2 LSB) at V

in Figure 6 and adjust the op amp

offset voltage until the ADC output code flickers between 1111

1111 1111 and 0000 0000 0000.

10kΩ

500Ω

10kΩ

IN1

AGND

AD7874*

*ADDITIONAL PINS OMITTED FOR CLARITY

INPUT

RANGE = ±10V

10kΩ

Figure 6. AD7874 Full-Scale Adjust Circuit

Gain error can be adjusted at either the first code transition

(ADC negative full scale) or the last code transition (ADC posi-

tive full scale). The trim procedures for both cases are as

follows:

Positive Full-Scale Adjust

Apply a voltage of +9.9927 V (FS/2 – 3/2 LSBs) at V

. Adjust

R2 until the ADC output code flickers between 0111 1111 1110

and 0111 1111 1111.

Negative Full-Scale Adjust

Apply a voltage of –9.9976 V ( –FS + 1/2 LSB) at V

and adjust

R2 until the ADC output code flickers between 1000 0000 0000

and 1000 0000 0001.

An alternative scheme for adjusting full-scale error in systems

which use an external reference is to adjust the voltage at the

REF IN pin until the full-scale error for any of the channels is

adjusted out. The good full-scale matching of the channels will

ensure small full-scale errors on the other channels.

TIMING AND CONTROL

Conversion is initiated on the AD7874 by asserting the

CONVST input. This CONVST input is an asynchronous input

which is independent of the ADC clock. This is essential for

applications where precise sampling in time is important. In

these applications, the signal sampling must occur at exactly

equal intervals to minimize errors due to sampling uncertainty

or jitter. In these cases, the

CONVST input is driven from a

timer or precise clock source. Once conversion is started,

CONVST should not be asserted again until conversion is com-

plete on all four channels.

In applications where precise time interval sampling is not criti-

cal, the

CONVST pulse can be generated from a microproces-

sor WRITE or READ line gated with a decoded address

(different to the AD7874

CS address). CONVST should not be

derived from a decoded address alone because very short

CONVST pulses (which may occur in some microprocessor sys-

tems as the address bus is changing at the start of an instruction

cycle) could initiate a conversion.

All four track/hold amplifiers go from track to hold on the rising

edge of the

CONVST pulse. The four track/hold amplifiers re-

main in their hold mode while all four channels are converted.

The rising edge of

CONVST also initiates a conversion on the

Channel 1 input voltage (V

IN1

). When conversion is complete

on Channel 1, its result is stored in Data Register 1, one of four

on-chip registers used to store the conversion results. When the

result from the first conversion is stored, conversion is initiated

on the voltage held by track/hold 2. When conversion has been

completed on the voltage held by track/hold 4 and its result is

stored in Data Register 4,

INT goes low to indicate that the

conversion process is complete.

The sequence in which the channel conversions takes place is

automatically taken care of by the AD7874. This means that the

user does not have to provide address lines to the AD7874 or

worry about selecting which channel is to be digitized.

Reading data from the device consists of four read operations to

the same microprocessor address. Addressing of the four

on-chip data registers is again automatically taken care of by the

AD7874.

AD7874

REV. C

–8–

The first read operation to the AD7874 after conversion always

accesses data from Data Register 1 (i.e., the conversion result

from the V

IN1

input). INT is reset high on the falling edge of

RD during this first read operation. The second read always ac-

cesses data from Data Register 2 and so on. The address pointer

is reset to point to Data Register 1 on the rising edge of

CONVST. A read operation to the AD7874 should not be at-

tempted during conversion. The timing diagram for the

AD7874 conversion sequence is shown in Figure 7.

CH1

DATA

CH2

DATA

CH3

DATA

CH4

DATA

INT

CONVST

HIGH-IMPEDANCE

TRACK/HOLDS GO

INTO HOLD

HIGH-

HIGH-Z

CONV

ACQUISITION

HIGH-

TIMES t

, t

, AND t

ARE THE SAME FOR ALL FOUR READ OPERATIONS.

Figure 7. AD7874 Timing Diagram

AD7874 DYNAMIC SPECIFICATIONS

The AD7874 is specified and 100% tested for dynamic perfor-

mance specifications as well as traditional dc specifications such

as Integral and Differential Nonlinearity. These ac specifications

are required for the signal processing applications such as

phased array sonar, adaptive filters and spectrum analysis.

These applications require information on the ADC’s effect on

the spectral content of the input signal. Hence, the parameters

for which the AD7874 is specified include SNR, harmonic dis-

tortion, intermodulation distortion and peak harmonics. These

terms are discussed in more detail in the following sections.

Signal-to-Noise Ratio (SNR)

SNR is the measured signal to noise ratio at the output of the

ADC. The signal is the rms magnitude of the fundamental.

Noise is the rms sum of all the nonfundamental signals up to

half the sampling frequency (fs/2) excluding dc. SNR is depen-

dent upon the number of quantization levels used in the digiti-

zation process; the more levels, the smaller the quantization

noise. The theoretical signal to noise ratio for a sine wave input

is given by

SNR = (6.02N + 1.76) dB (1)

where N is the number of bits.

Thus for an ideal 12-bit converter, SNR = 74 dB.

The output spectrum from the ADC is evaluated by applying a

sine wave signal of very low distortion to the V

input which is

sampled at a 29 kHz sampling rate. A Fast Fourier Transform

(FFT) plot is generated from which the SNR data can be ob-

tained. Figure 8 shows a typical 2048 point FFT plot of the

AD7874BN with an input signal of 10 kHz and a sampling

frequency of 29 kHz. The SNR obtained from this graph is

73.2 dB. It should be noted that the harmonics are taken into

account when calculating the SNR.

Figure 8. AD7874 FFT Plot

Effective Number of Bits

The formula given in Equation 1 relates the SNR to the number

of bits. Rewriting the formula, as in Equation 2, it is possible to

get a measure of performance expressed in effective number of

bits (N).

N =

SNR −1. 76

6.02

(2)

The effective number of bits for a device can be calculated di-

rectly from its measured SNR.

Figure 9 shows a typical plot of effective number of bits versus

frequency for an AD7874BN with a sampling frequency of

29 kHz. The effective number of bits typically falls between

11.75 and 11.87 corresponding to SNR figures of 72.5 dB and

73.2 dB.

Figure 9. Effective Numbers of Bits vs. Frequency

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AD7874BRZ

Mfr. #:

Buy AD7874BRZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC Data Acquisition System IC 12-Bit

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AD7874BRZ

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