DS1743P-100+ Datasheet DS1743WP-120+, DS1743-70+, DS1743-100IND+ | P4-P6

DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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PACKAGES

The DS1743 is available in two packages: the 28-pin DIP and the 34-pin PowerCap module. The 28-pin

DIP-style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin

PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)

that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the

DS1743P after the completion of the surface-mount process. Mounting the PowerCap after the surface-

mount process prevents damage to the crystal and battery due to the high temperatures required for solder

reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap

are ordered separately and shipped in separate containers. The part number for the PowerCap is

DS9034PCX.

TIME AND DATE OPERATION

The time and date information is obtained by reading the appropriate register bytes. Table 2 shows the

RTC registers. The time and date are set or initialized by writing the appropriate register bytes. The

contents of the time and date registers are in the BCD format. The day-of-week register increments at

midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1

equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined

operation.

CLOCK OPERATIONS-READING THE CLOCK

While the double-buffered register structure reduces the chance of reading incorrect data, internal updates

to the DS1743 clock registers should be halted before clock data is read to prevent reading of data in

transition. However, halting the internal clock register updating process does not affect clock accuracy.

Updating is halted when a 1 is written into the read bit, bit 6 of the century register (see Table 2). As long

as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count that

is day, date, and time that was current at the moment the halt command was issued. However, the internal

clock registers of the double-buffered system continue to update so that the clock accuracy is not affected

by the access of data. All the DS1743 registers are updated simultaneously after the internal clock register

updating process has been re-enabled. Updating is within a second after the read bit is written to 0.

The READ bit must be a zero for a minimum of 500s to ensure the external registers are updated.

DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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Figure 1. Block Diagram

Table 1. Truth Table

CE2

OE WE

MODE DQ POWER

X X X Deselect High-Z Standby

X V

X X Deselect High-Z Standby

X V

Write Data In Active

Read Data Out Active

> V

Read High-Z Active

< V

X X X X Deselect High-Z CMOS Standby

X X X X Deselect High-Z

Data-Retention

Mode

SETTING THE CLOCK

As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read

bit, halts updates to the DS1743 registers. The user can then load them with the correct day, date and time

data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock

counters and allows normal operation to resume.

STOPPING AND STARTING THE CLOCK OSCILLATOR

The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off

to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see

Table 2. Setting it to a 1 stops the oscillator.

FREQUENCY TEST BIT

As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to

logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512Hz. When the

seconds register is being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for

access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and

stable).

Dallas

Semiconductor

DS1743

DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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CLOCK ACCURACY (DIP MODULE)

The DS1743 is guaranteed to keep time accuracy to within 1 minute per month at +25C. The RTC is

calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require

additional calibration. For this reason, methods of field clock calibration are not available and not

necessary. The electrical environment also affects clock accuracy, so caution should be taken to place the

RTC in the lowest-level EMI section of the PC board layout. For additional information, please refer to

Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.

CLOCK ACCURACY (PowerCap MODULE)

The DS1743 and DS9034PCX are each individually tested for accuracy. Once mounted together, the

module will typically keep time accuracy to within 1.53 minutes per month (35ppm) at +25°C. The

electrical environment also affects clock accuracy, so caution should be taken to place the RTC in the

lowest-level EMI section of the PC board layout. For additional information, please refer to Application

Note 58: Crystal Considerations with Dallas Real-Time Clocks.

Table 2. Register Map

DATA

ADDRESS

FUNCTION RANGE

1FFF 10 Year Year Year 00–99

1FFE X X X

Month

Month Month 01–12

1FFD X X 10 Date Date Date 01–31

1FFC BF FT X X X Day Day 01–07

1FFB X X 10 Hour Hour Hour 00–23

1FFA X 10 Minutes Minutes Minutes 00–59

1FF9

OSC

10 Seconds Seconds Seconds 00–59

1FF8 W R 10 Century Century Control 00–39

OSC = STOP BIT

R = READ BIT FT = FREQUENCY TEST

W = WRITE BIT X = SEE NOTE BELOW BF = BATTERY FLAG

Note: All indicated “X” bits must be set to “0” when written to ensure proper clock operation.

RETRIEVING DATA FROM RAM OR CLOCK

The DS1743 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE

(chip enable) is low. The device architecture allows ripple-through access to any of the address locations in

the NV SRAM. Valid data will be available at the DQ pins within t

after the last address input is stable,

providing that the, CE and OE access times and states are satisfied. If CE, or OE access times and states

are not met, valid data will be available at the latter of chip enable access (t

CEA

) or at output enable access

time (t

CEA

). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs are

activated before t

, the data lines are driven to an intermediate state until t

. If the address inputs are

changed while CE and OE remain valid, output data will remain valid for output data hold time (t

) but

will then go indeterminate until the next address access.

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