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74AUP2G86GS,115

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
74AUP2G86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 24 January 2013 15 of 21
NXP Semiconductors
74AUP2G86
Low-power dual 2-input EXCLUSIVE-OR gate
Fig 14. Package outline SOT902-2 (XQFN8)
References
Outline
version
European
projection
Issue date
IEC JEDEC JEITA
SOT902-2 - - -
MO-255
- - -
sot902-2_po
10-11-02
11-03-31
Unit
(1)
mm
max
nom
min
0.5 0.05
0.00
1.65
1.60
1.55
1.65
1.60
1.55
0.55 0.5
0.15
0.10
0.05
0.1 0.05
A
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
XQFN8: plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 x 1.6 x 0.5 mm
SOT902-2
A
1
b
0.25
0.20
0.15
DEee
1
L
0.35
0.30
0.25
L
1
vw
0.05
yy
1
0.05
0 1 2 mm
scale
terminal 1
index area
B
A
D
E
X
C
y
C
y
1
terminal 1
index area
3
L
L
1
b
e
1
e
AC
B
v
Cw
2
1
5
6
7
metal area
not for soldering
8
4
A
1
A
detail X
74AUP2G86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 24 January 2013 16 of 21
NXP Semiconductors
74AUP2G86
Low-power dual 2-input EXCLUSIVE-OR gate
Fig 15. Package outline SOT1116 (XSON8)
References
Outline
version
European
projection
Issue date
IEC JEDEC JEITA
SOT1116
sot1116_po
10-04-02
10-04-07
Unit
mm
max
nom
min
0.35 0.04 1.25
1.20
1.15
1.05
1.00
0.95
0.55 0.3
0.40
0.35
0.32
A
(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm
SOT1116
A
1
b
0.20
0.15
0.12
DEee
1
L
0.35
0.30
0.27
L
1
0 0.5 1 mm
scale
terminal 1
index area
E
D
(4×)
(2)
(8×)
(2)
A
1
A
e
1
e
1
e
1
e
L
L
1
b
4321
5678
74AUP2G86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 24 January 2013 17 of 21
NXP Semiconductors
74AUP2G86
Low-power dual 2-input EXCLUSIVE-OR gate
Fig 16. Package outline SOT1203 (XSON8)
References
Outline
version
European
projection
Issue date
IEC JEDEC JEITA
SOT1203
sot1203_po
10-04-02
10-04-06
Unit
mm
max
nom
min
0.35 0.04 1.40
1.35
1.30
1.05
1.00
0.95
0.55 0.35
0.40
0.35
0.32
A
(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm
SOT1203
A
1
b
0.20
0.15
0.12
DEee
1
L
0.35
0.30
0.27
L
1
0 0.5 1 mm
scale
terminal 1
index area
E
D
(4×)
(2)
(8×)
(2)
A
A
1
e
L
L
1
b
e
1
e
1
e
1
1
8
2
7
3
6
4
5
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

74AUP2G86GS,115

Mfr. #:
Buy 74AUP2G86GS,115
Manufacturer:
Nexperia
Description:
Logic Gates OR 4.6 V 20 mA
Lifecycle:
New from this manufacturer.
Delivery:
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