MT8809 Data Sheet
6
Zarlink Semiconductor Inc.
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5 ns.
‡ Typical figures are at 25
°C and are for design aid only; not guaranteed and not subject to production testing.
Å¿Refer to Appendix, Fig. A.7 for test circuit.
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
AC Electrical Characteristics
†
- Control and I/O Timings- V
DC
is the external DC offset applied at the analog I/O pins.
Voltages are with respect to V
DD
= 5 V, V
DC
= 0 V, V
SS
= -7 V, unless otherwise stated.
Characteristics Sym. Min. Typ.
‡
Max. Units Test Conditions
1 Control Input crosstalk to switch
(for CS
, DATA, STROBE,
Address)
CX
talk
30 mVpp V
IN
=3V+V
DC
squarewave;
R
IN
=1 kΩ, R
L
=1 kΩ.
See Appendix, Fig. A.6
2 Digital Input Capacitance C
DI
10 pF f = 1 MHz
3 Switching Frequency F
O
20 MHz
4 Setup Time DATA to STROBE
t
DS
10 ns R
L
= 1 kΩ, C
L
= 50 pF ¿
Å
5 Hold Time DATA to STROBE t
DH
10 ns R
L
= 1 kΩ, C
L
= 50 pF
Å¿
6 Setup Time Address to STROBE
t
AS
10 ns R
L
= 1 kΩ, C
L
= 50 pF
Å¿
7 Hold Time Address to STROBE
t
AH
10 ns R
L
= 1 kΩ, C
L
= 50 pF
Å¿
8 Setup Time CS
to STROBE t
CSS
10 ns R
L
= 1 kΩ, C
L
= 50 pF
Å¿
9 Hold Time CS
to STROBE t
CSH
10 ns R
L
= 1 kΩ, C
L
= 50 pF
¿Å
10 STROBE Pulse Width t
SPW
20 ns R
L
= 1 kΩ, C
L
= 50 pF
¿Å
11 RESET Pulse Width t
RPW
40 ns R
L
= 1 kΩ, C
L
= 50 pF
Å¿
12 STROBE
to Switch Status Delay t
S
40 100 ns R
L
= 1 kΩ, C
L
=50 pF
Å¿
13 DATA to Switch Status Delay t
D
50 100 ns R
L
= 1 kΩ, C
L
= 50 pF
Å¿
14 RESET
to Switch Status Delay t
R
35 100 ns R
L
= 1 kΩ, C
L
= 50 pF
¿Å
CS
RESET
STROBE
ADDRESS
DATA
SWITCH*
t
CSS
t
CSH
t
RPW
t
SPW
t
AS
t
AH
t
DS
t
DH
t
D
t
S
t
R
t
R
ON
OFF
50% 50%
50% 50%
50% 50% 50%
50% 50%
50% 50%
