N04L63W1AB27IT Datasheet N04L63W1AT27IT, N04L63W1AT27I, N04L63W1AB27I | P1-P3

N04L63W1A

July 2008 - Rev. 13 N04L63W1A/D

4Mb Ultra-Low Power Asynchronous CMOS SRAM

256K × 16 bit

Overview

The N04L63W1A is an integrated memory device

containing a 4 Mbit Static Random Access Memory

organized as 262,144 words by 16 bits. The device

is designed and fabricated using ON

Semiconductor’s advanced CMOS technology to

provide both high-speed performance and ultra-low

power. The device operates with a single chip

enable (CE

) control and output enable (OE) to

allow for easy memory expansion. Byte controls

(UB

and LB) allow the upper and lower bytes to be

accessed independently. The N04L63W1A is

optimal for various applications where low-power is

critical such as battery backup and hand-held

devices. The device can operate over a very wide

temperature range of -40

o

C to +85

o

C and is

available in JEDEC standard packages compatible

with other standard 256Kb x 16 SRAMs.

Features

• Single Wide Power Supply Range

2.3 to 3.6 Volts

• Very low standby current

4.0µA at 3.0V (Typical)

• Very low operating current

2.0mA at 3.0V and 1µs (Typical)

• Very low Page Mode operating current

0.8mA at 3.0V and 1µs (Typical)

• Simple memory control

Single Chip Enable (CE

)

Output Enable (OE

) for memory expansion

• Low voltage data retention

Vcc = 1.8V

• Very fast output enable access time

25ns OE

access time

• Automatic power down to standby mode

• TTL compatible three-state output driver

• Compact space saving BGA package avail-

able

Pin Configurations

Product Family

Part Number Package Type

Operating

Temperature

Power

Supply

(Vcc)

Speed

Options

Standby

Current (I

SB

),

Typical

Operating

Current (Icc),

Typical

N04L63W1AB 48 - BGA

-40

o

C to +85

o

C

2.3V - 3.6V

70ns @ 2.7V

55ns @ 2.7V

4 µA2 mA @ 1MHz

N04L63W1AT 44 - TSOP II

N04L63W1AB2 48 - BGA Green

N04L63W1AT2 44 - TSOP II Green

ONE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

A

4

A3

A2

A1

A0

CE

I/O0

I/O1

I/O2

I/O3

VCC

VSS

I/O

4

I/O5

I/O6

I/O7

WE

A16

A15

A14

A13

A12

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

A

5

A6

A7

OE

UB

LB

I/O15

I/O14

I/O13

I/O12

VSS

VCC

I/O

11

I/O10

I/O9

I/O8

NC

A

8

A9

A10

A11

A

17

N04L63W1A

TSOP-II

123456

A

LB OE

A

0

A

1

A

2

NC

B

I/O

8

UB

A

3

A

4

CE

I/O

0

C

I/O

9

I/O

10

A

5

A

6

I/O

1

I/O

2

D

V

SS

I/O

11

A

17

A

7

I/O

3

V

CC

E

V

CC

I/O

12

NC

A

16

I/O

4

V

SS

F

I/O

14

I/O

13

A

14

A

15

I/O

5

I/O

6

G

I/O

15

NC

A

12

A

13

WE

I/O

7

H

NC

A

8

A

9

A

10

A

11

NC

48 Pin BGA (top)

6 x 8 mm

Pin Descriptions

Pin Name Pin Function

A

0

-A

17

Address Inputs

WE

Write Enable Input

CE

Chip Enable Input

OE

Output Enable Input

LB

Lower Byte Enable Input

UB

Upper Byte Enable Input

I/O

0

-I/O

15

Data Inputs/Outputs

NC Not Connected

V

CC

Power

V

SS

Ground

Rev. 13 | Page 2 of 10 | www.onsemi.com

N04L63W1A

Functional Block Diagram

Functional Description

CE WE OE UB LB

I/O

0

- I/O

15

1

1. When UB and LB are in select mode (low), I/O

0

- I/O

15

are affected as shown. When LB only is in the select mode only I/O

0

- I/O

7

are affected as shown. When UB is in the select mode only I/O

8

- I/O

15

are affected as shown.

MODE POWER

HXXXX High Z

Standby

2

2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally

isolated from any external influence and disabled from exerting any influence externally.

Standby

L X X H H High Z

Standby

2

Standby

LL

X

3

3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.

L

1

L

1

Data In

Write

3

Active

LHL

L

1

L

1

Data Out

Read

Active

LHH

L

1

L

1

High Z Active Active

Capacitance

1

1. These parameters are verified in device characterization and are not 100% tested

Item Symbol Test Condition Min Max Unit

Input Capacitance

C

IN

V

IN

= 0V, f = 1 MHz, T

A

= 25

o

C

8pF

I/O Capacitance

C

I/O

V

IN

= 0V, f = 1 MHz, T

A

= 25

o

C

8pF

Address

Inputs

A0 - A3

Address

Inputs

A4 - A17

Word

Address

Decode

Logic

16K Page

x 16 word

x 16 bit

RAM Array

Word Mux

Input/

Output

Mux

and

Buffers

Page

Address

Decode

Logic

Control

Logic

CE

WE

OE

UB

LB

I/O0 - I/O7

I/O8 - I/O15

Rev. 13 | Page 3 of 10 | www.onsemi.com

N04L63W1A

Absolute Maximum Ratings

1

1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the operating section of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item Symbol Rating Unit

Voltage on any pin relative to V

SS

V

IN,OUT

–0.3 to V

CC

+0.3

V

Voltage on V

CC

Supply Relative to V

SS

V

CC

–0.3 to 4.5 V

Power Dissipation

P

D

500 mW

Storage Temperature

T

STG

–40 to 125

o

C

Operating Temperature

T

A

-40 to +85

o

C

Soldering Temperature and Time

T

SOLDER

260

o

C, 10sec

o

C

Operating Characteristics (Over Specified Temperature Range)

Item Symbol Test Conditions Min.

Typ

1

1. Typical values are measured at Vcc=Vcc Typ., T

A

=25°C and are not 100% tested.

Max Unit

Supply Voltage

V

CC

2.3 3.0 3.6 V

Data Retention Voltage

V

DR

Chip Disabled

2

1.8 V

Input High Voltage

V

IH

1.8

V

CC

+0.3

V

Input Low Voltage

V

IL

–0.3 0.6 V

Output High Voltage

V

OH

I

OH

= 0.2mA V

CC

–0.2

V

Output Low Voltage

V

OL

I

OL

= -0.2mA

0.2 V

Input Leakage Current

I

LI

V

IN

= 0 to V

CC

0.5 µA

Output Leakage Current

I

LO

OE = V

IH

or Chip Disabled

0.5 µA

Read/Write Operating Supply Current

@ 1 µs Cycle Time

2

2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive

output capacitance expected in the actual system.

I

CC1

V

CC

=3.6 V, V

IN

=V

IH

or V

IL

Chip Enabled, I

OUT

= 0

2.0 3.0 mA

Read/Write Operating Supply Current

@ 70ns Cycle Time

2

I

CC2

V

CC

=3.6 V, V

IN

=V

IH

or V

IL

Chip Enabled, I

OUT

= 0

10 16.0 mA

Page Mode Operating Supply Current

@ 70ns Cycle Time

2

(Refer to Power

Savings with Page Mode Operation

diagram)

I

CC3

V

CC

=3.6 V, V

IN

=V

IH

or V

IL

Chip Enabled, I

OUT

= 0

4mA

Read/Write Quiescent Operating Sup-

ply Current

3

3. This device assumes a standby mode if the chip is disabled (CE high or UB and LB high). In order to achieve low standby current

all inputs must be within 0.2 volts of either VCC or VSS

I

CC4

V

CC

=3.6 V, V

IN

=V

IH

or V

IL

Chip Enabled, I

OUT

= 0,

f = 0

3.0 mA

Maximum Standby Current

3

I

SB1

V

IN

= V

CC

or 0V

Chip Disabled

t

A

= 85

o

C, VCC = 3.6 V

4.0 20 µA

Maximum Data Retention Current

3

I

DR

V

CC

= 1.8V, V

IN

= V

CC

or 0

Chip Disabled, t

A

= 85

o

C

10 µA

N04L63W1AB27IT

N04L63W1AB27IT

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