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LT3481EDD#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LT3481
13
3481fc
A fi nal precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LT3481. A ceramic
input capacitor combined with trace or cable inductance
forms a high quality (under damped) tank circuit. If the
LT3481 circuit is plugged into a live supply, the input volt-
age can ring to twice its nominal value, possibly exceeding
the LT3481’s rating. This situation is easily avoided (see
the Hot Plugging Safely section).
Frequency Compensation
The LT3481 uses current mode control to regulate the
output. This simplifi es loop compensation. In particular, the
LT3481 does not require the ESR of the output capacitor
for stability, so you are free to use ceramic capacitors to
achieve low output ripple and small circuit size. Frequency
compensation is provided by the components tied to the
V
C
pin, as shown in Figure 2. Generally a capacitor (C
C
)
and a resistor (R
C
) in series to ground are used. In addi-
tion, there may be lower value capacitor in parallel. This
capacitor (C
F
) is not part of the loop compensation but
is used to fi lter noise at the switching frequency, and is
required only if a phase-lead capacitor is used or if the
output capacitor has high ESR.
Loop compensation determines the stability and transient
performance. Designing the compensation network is
a bit complicated and the best values depend on the
application and in particular the type of output capacitor.
A practical approach is to start with one of the circuits in
this data sheet that is similar to your application and tune
the compensation network to optimize the performance.
Stability should then be checked across all operating
conditions, including load current, input voltage and
temperature. The LT1375 data sheet contains a more
thorough discussion of loop compensation and describes
how to test the stability using a transient load. Figure 2
shows an equivalent circuit for the LT3481 control loop.
The error amplifi er is a transconductance amplifi er with
fi nite output impedance. The power section, consisting
of the modulator, power switch and inductor, is modeled
as a transconductance amplifi er generating an output
current proportional to the voltage at the V
C
pin. Note that
the output capacitor integrates this current, and that the
capacitor on the V
C
pin (C
C
) integrates the error amplifi er
output current, resulting in two poles in the loop. In most
cases a zero is required and comes from either the output
capacitor ESR or from a resistor R
C
in series with C
C
.
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. A phase lead
capacitor (C
PL
) across the feedback divider may improve
the transient response. Figure 3 shows the transient
response when the load current is stepped from 500mA
to 1500mA and back to 500mA.
–
+
1.265V
SW
V
C
GND
3Meg
LT3481
3481 F02
R1
OUTPUT
ESR
C
F
C
C
R
C
ERROR
AMPLIFIER
FB
R2
C1
C1
CURRENT MODE
POWER STAGE
g
m
= 3.5mho
g
m
=
330μmho
+
POLYMER
OR
TANTALUM
CERAMIC
C
PL
Figure 3. Transient Load Response of the LT3481 Front Page
Application as the Load Current is Stepped from 500mA to
1500mA. V
OUT
= 3.3V
Figure 2. Model for Loop Response
3481 F03
I
L
1A/DIV
V
OUT
100mV/DIV
10μs/DIV
V
OUT
= 12V; FRONT PAGE APPLICATION
APPLICATIONS INFORMATION
LT3481
14
3481fc
Burst Mode Operation
To enhance effi ciency at light loads, the LT3481 auto-
matically switches to Burst Mode operation which keeps
the output capacitor charged to the proper voltage while
minimizing the input quiescent current. During Burst Mode
operation, the LT3481 delivers single cycle bursts of current
to the output capacitor followed by sleep periods where
the output power is delivered to the load by the output
capacitor. In addition, V
IN
and BIAS quiescent currents are
reduced to typically 20μA and 50μA respectively during
the sleep time. As the load current decreases towards a
no load condition, the percentage of time that the LT3481
operates in sleep mode increases and the average input
current is greatly reduced resulting in higher effi ciency.
See Figure 4.
boost diode can be tied to the input (Figure 5c), or to
another supply greater than 2.8V. The circuit in Figure 5a
is more effi cient because the BOOST pin current and BIAS
pin quiescent current comes from a lower voltage source.
You must also be sure that the maximum voltage ratings
of the BOOST and BIAS pins are not exceeded.
BOOST and BIAS Pin Considerations
Capacitor C3 and the internal boost Schottky diode (see
the Block Diagram) are used to generate a boost volt-
age that is higher than the input voltage. In most cases
a 0.22μF capacitor will work well. Figure 2 shows three
ways to arrange the boost circuit. The BOOST pin must be
more than 2.3V above the SW pin for best effi ciency. For
outputs of 3V and above, the standard circuit (Figure 5a)
is best. For outputs between 2.8V and 3V, use a 1μF boost
capacitor. A 2.5V output presents a special case because it
is marginally adequate to support the boosted drive stage
while using the internal boost diode. For reliable BOOST pin
operation with 2.5V outputs use a good external Schottky
diode (such as the ON Semi MBR0540), and a 1μF boost
capacitor (see Figure 5b). For lower output voltages the
V
IN
BOOST
SW
BD
V
IN
V
OUT
4.7μF
GND
LT3481
V
IN
BOOST
SW
BD
V
IN
V
OUT
4.7μF
C3
D2
GND
LT3481
V
IN
BOOST
SW
BD
V
IN
V
OUT
4.7μF
C3
GND
LT3481
3481 FO5
(5a) For V
OUT
> 2.8V
(5b) For 2.5V < V
OUT
< 2.8V
(5c) For V
OUT
< 2.5V
C3
The minimum operating voltage of an LT3481 application
is limited by the minimum input voltage (3.6V) and by the
maximum duty cycle as outlined in a previous section. For
proper startup, the minimum input voltage is also limited
by the boost circuit. If the input voltage is ramped slowly,
or the LT3481 is turned on with its RUN/SS pin when the
output is already in regulation, then the boost capacitor
Figure 5. Three Circuits For Generating The Boost Voltage
Figure 4. Burst Mode Operation
3481 F04
I
L
0.5A/DIV
V
SW
5V/DIV
V
OUT
10mV/DIV
5μs/DIV
V
IN
= 12V; FRONT PAGE APPLICATION
I
LOAD
= 10mA
APPLICATIONS INFORMATION
LT3481
15
3481fc
may not be fully charged. Because the boost capacitor is
charged with the energy stored in the inductor, the circuit
will rely on some minimum load current to get the boost
circuit running properly. This minimum load will depend
on input and output voltages, and on the arrangement of
the boost circuit. The minimum load generally goes to
zero once the circuit has started. Figure 6 shows a plot
of minimum load to start and to run as a function of input
voltage. In many cases the discharged output capacitor
will present a load to the switcher, which will allow it to
start. The plots show the worst-case situation where V
IN
is ramping very slowly. For lower start-up voltage, the
boost diode can be tied to V
IN
; however, this restricts the
input range to one-half of the absolute maximum rating
of the BOOST pin.
At light loads, the inductor current becomes discontinu-
ous and the effective duty cycle can be very high. This
reduces the minimum input voltage to approximately
300mV above V
OUT
. At higher load currents, the inductor
current is continuous and the duty cycle is limited by the
maximum duty cycle of the LT3481, requiring a higher
input voltage to maintain regulation.
Soft-Start
The RUN/SS pin can be used to soft-start the LT3481,
reducing the maximum input current during start-up.
The RUN/SS pin is driven through an external RC fi lter to
create a voltage ramp at this pin. Figure 7 shows the start-
up and shutdown waveforms with the soft-start circuit.
By choosing a large RC time constant, the peak start-up
current can be reduced to the current that is required to
regulate the output, with no overshoot. Choose the value
of the resistor so that it can supply 20μA when the RUN/SS
pin reaches 2.3V.
Synchronization
The internal oscillator of the LT3481 can be synchronized
to an external 275kHz to 475kHz clock by using a 5pF
to 20pF capacitor to connect the clock signal to the RT
pin. The resistor tying the RT pin to ground should be
chosen such that the LT3481 oscillates 20% lower than
the intended synchronization frequency (see Setting the
Switching Frequency section).
The LT3481 should not be synchronized until its output
is near regulation as indicated by the PG fl ag. This can be
done with the system microcontroller/microprocessor or
with a discrete circuit by using the PG output. If a sync
signal is applied while the PG is low, the LT3481 may
exhibit erratic operation. See Typical Applications.
When applying a sync signal, positive clock transitions
reset LT3481’s internal clock and negative transitions
initiate a switch cycle. The amplitude of the sync signal
must be at least 2V. The sync signal duty cycle can range
Figure 7. To Soft-Start the LT3481, Add a Resisitor
and Capacitor to the RUN/SS Pin
Figure 6. The Minimum Input Voltage Depends on
Output Voltage, Load Current and Boost Circuit
3481 F06
LOAD CURRENT (A)
0.001
INPUT VOLTAGE (V)
4.0
4.5
5.0
10
3.5
3.0
2.0
0.01
0.1
1
2.5
6.0
5.5
TO START
TO RUN
V
OUT
= 3.3V
T
A
= 25°C
L = 4.7μ
f = 800 kHz
LOAD CURRENT (A)
0.001
INPUT VOLTAGE (V)
5.0
6.0
7.0
10
4.0
2.0
0.01
0.1
1
3.0
8.0
TO START
TO RUN
V
OUT
= 5.0V
T
A
= 25 °C
L = 4.7μ
f = 800 kHz
3481 F07
I
L
1A/DIV
V
RUN/SS
2V/DIV
V
OUT
2V/DIV
RUN/SS
GND
0.22μF
RUN
15k
2ms/DIV
APPLICATIONS INFORMATION
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LT3481EDD#PBF

Mfr. #:
Buy LT3481EDD#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 36V, 2A (Iout), 2.8MHz Step-Down Switching Regulator in DFN
Lifecycle:
New from this manufacturer.
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