OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LTC1771ES8#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
10
LTC1771
continuous mode, I
GATECHG
= fQ
P
where Q
P
is the gate
charge of the internal switch. Both the DC bias and gate
charge losses are proportional to V
IN
and thus their
effects will be more pronounced at higher supply
voltages.
3. I
2
R losses are predicted from the internal switch, induc-
tor and current sense resistor. In continuous mode the
average output current flows through L but is “chopped”
between the P-channel MOSFET in series with R
SENSE
and the output diode. The MOSFET R
DS(ON)
plus R
SENSE
multiplied by the duty cycle can be summed with the
resistance of L to obtain I
2
R losses.
4. The catch diode loss is proportional to the forward drop
as the diode conducts current during the off-time and is
more pronounced at high supply voltages where the
off-time is long. However, as discussed in the Catch
Diode section, diodes with lower forward drops often
have higher leakage currents, so although efficiency is
improved, the no-load supply current will increase. The
diode loss is calculated by multiplying the forward
voltage drop times the diode duty cycle multiplied by
the load current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses, and inductor core losses, generally account for
less than 2% total additional loss.
Output Voltage Programming
The output voltage is programmed with an external divider
from V
OUT
to V
FB
(Pin 1) as shown in Figure 2. The
regulated voltage is determined by:
V
R
R
OUT
=+
123 1
2
1
.
To minimize no-load supply current, resistor values in the
megohm range should be used. The increase in supply
current due to the feedback resistors can be calculated
from:
∆=
+
I
V
RR
V
V
OUT OUT
IN
VIN
12
A 5pF feedforward capacitor across R2 is recommended
to minimize output voltage ripple in Burst Mode operation.
Run/Soft-Start Function
The RUN/SS pin is a dual purpose pin that provides the
soft- start function and a means to shut down the LTC1771.
Soft-start reduces the input surge current from V
IN
by
gradually increasing the internal current limit. Power
supply sequencing can also be accomplished using
this pin.
An internal 1µA current source charges up an external
capacitor C
SS
. When the voltage on the RUN/SS reaches
1V, the LTC1771 begins operating. As the voltage on the
RUN/SS continues to ramp from 1V to 2.2V, the internal
current limit is also ramped at a proportional linear rate.
The current limits begins near 40% maximum load at
V
RUN/SS
= 1V and ends at maximum load at V
RUN/SS
=
2.2V. The output current thus ramps up slowly, reducing
the starting surge current required from the input power
supply. If the RUN/SS has been pulled all the way to
ground, there will be a delay before the current limit starts
increasing and is given by:
t
DELAY
≈ C
SS
/I
CHG
where I
CHG
≅ 1µA. Pulling the RUN/SS pin below 0.5V
puts the LTC1771 into a low quiescent current shutdown
(I
Q
< 2µA).
Foldback Current Limiting
As described in the Catch Diode Selection, the worst-case
dissipation for diode occurs with a short-circuit output,
when the diode conducts the current limit value almost
continuously. In most applications this will not cause
excessive heating, even for extended fault intervals. How-
ever, when heat sinking is at a premium or higher forward
voltage drop diodes are being used, foldback current
V
FB
R2
C
FF
5pF
R1
V
OUT
1771 F02
LTC1771
GND
Figure 2. LTC1771 Adjustable Configuaration
APPLICATIO S I FOR ATIO
WUUU
11
LTC1771
limiting should be added to reduce the current in propor-
tion to the severity of the fault.
Foldback current limiting is implemented by adding two
diodes in series between the output and the I
TH
pin as
shown in the Functional Diagram. In a hard short (V
OUT
=
0V) the current will be reduced to approximately 25% of
the maximum output current.
Minimum On-Time Considerations
Minimum on-time t
ON(MIN)
is the smallest amount of time
that the LTC1771 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the amount of gate charge required to turn on the
P-channel MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
tt
VV
VV
t
ON OFF
OUT D
IN OUT
ON MIN
=
+
−
>
()
where t
OFF
= 3.5µs and t
ON(MIN)
is generally about 0.4µs
for the LTC1771.
As the on-time approaches t
ON(MIN)
, the LTC1771 will
remain in Burst Mode operation for an increasingly larger
portion of the load range (see Figure 3) and at or below
t
ON(MIN)
will remain in Burst Mode operation 100% of the
time. The output voltage will continue to be regulated, but
the ripple current and ripple voltage will increase.
Mode Pin
Burst Mode operation is disabled by pulling MODE (Pin 8)
below 0.5V. Disabling Burst Mode operation provides a
low noise output spectrum, useful for reducing both audio
and RF interference. It does this by keeping the frequency
constant (for fixed V
IN
) down to much lower load current
(1% to 2% of I
MAX
) and reducing the amount of output
voltage and current ripple at light loads. When Burst Mode
operation is disabled, efficiency is reduced at light loads
and no load supply current increases to 175µA.
Low Supply Operation
Although the LTC1771 can function down to 2.8V, the
maximum allowable output current is reduced when V
IN
decreases below 3.2V. Figure 4 shows the amount of
change as the supply is reduced below 3.2V, where 100%
of maximum load equals 0.1/R
SENSE
. To ensure adequate
output current at V
IN
< 3.2V, simply lower R
SENSE
by the
same percentage as the current reduction in Figure 4.
APPLICATIO S I FOR ATIO
WUUU
ON-TIME (µs)
0
% OF MAXIMUM LOAD
60
80
100
2.0
1771 F03
40
20
0
0.5
1.0
1.5
2.5
Figure 3. Burst Threshold vs On-Time
INPUT VOLTAGE (V)
2.5
100
120
140
4.0 4.5
1771 F04
80
60
3.0 3.5 5.0
40
20
0
MAXIMUM LOAD (%)
Figure 4. Maximum Load vs Input Voltage
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1771. These items are also illustrated graphically in
the layout diagram of Figure 5. Check the following in your
layout:
1. Is the Schottky diode
closely
connected to the drain of
the external MOSFET and the input cap ground?
12
LTC1771
2. Is the 0.1µF input decoupling capacitor
closely
con-
nected between V
IN
(Pin 6) and ground (Pin 4)? This
capacitor carries the high frequency peak currents.
3. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1 and R2 must be
connected between the (+) plate of C
OUT
and signal
ground. Locate the feedback resistors right next to the
LTC1771. The V
FB
line should not be routed close to any
nodes with high slew rates.
4. Is the 1000pF decoupling capacitor for the current
sense resistor connected as close as possible to Pins 6
and 7? Ensure accurate current sensing with Kelvin
connections to the sense resistor.
5. Is the (+) plate of C
IN
closely
connected to the sense
resistor ? This capacitor provides the AC current to the
MOSFET.
6. Are the signal and power grounds segregated? The
signal ground consists of the (–) plate of C
OUT
, Pin 4 of
the LTC1771 and the resistive divider. The power ground
consists of the Schottky diode anode and the (–) plate
of C
IN
which should have as short lead lengths as
possible.
7. Keep the switching node (SW) and the gate node
(PGATE) away from sensitive small signal nodes, espe-
cially the voltage sensing feedback pin (V
FB
), and mini-
mize their PC trace area.
Design Example
As a design example, assume V
IN
= 10V (nominal), V
IN
=
15V
(MAX)
, V
OUT
= 3.3V, and I
MAX
= 2A. With this informa-
tion, we can easily calculate all the important components.
R
SENSE
= 100mV/2A = 0.05Ω
To optimize low current efficiency, MODE pin is tied to V
IN
to enable Burst Mode operation, thus the minimum induc-
tance necessary is:
L
MIN
= 70µH(3.3V + 0.5)(0.05Ω) = 13.3µH
15µH is chosen for the application.
∆=
+
=Is
VV
H
A
L
35
33 05
15
089.
..
.µ
µ
For the feedback resistors, choose R1 = 1M to minimize
supply current. R2 can then be calculated to be:
R2 = (V
OUT
/1.23 – 1) • R1 = 1.68M
Assume that the MOSFET dissipation is to be limited to
P
P
= 0.25W.
If T
A
= 70°C and the thermal resistance of the MOSFET is
83°C/W, then the junction temperatures will be 91°C and
δ
P
= 0.33. The required R
DS(ON)
for the MOSFET can now
be calculated:
Since the gate of the MOSFET will see the full input voltage,
a MOSFET must be selected whose V
GS(MAX)
> 15V. A
P-channel MOSFET that meets both the V
GS(MAX)
and
R
DS(ON)
requirement is the Si6447DQ.
The most stringent requirement for the Schottky diode
occurs when V
OUT
= 0V (i.e., short circuit) at maximum
V
IN
. In this case the worst-case dissipation rises to:
PI V
V
VV
SC AVG D
IN
IN D
D
=
()
+
()
Figure 5. LTC1771 Layout Diagram
APPLICATIO S I FOR ATIO
WUUU
RUN/SS
I
TH
V
FB
GND
V
OUT
R
ITH
C
ITH
C
FF
0.1µF
Q1
D1
R2
R1
1
2
3
4
8
7
6
5
1771 F05
C
SS
C
IN
MODE
MODE
SENSE
V
IN
PGATE
LTC1771
BOLD LINES INDICATE HIGH CURRENT PATHS
+
C
OUT
L
+
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LTC1771ES8#TRPBF

Mfr. #:
Buy LTC1771ES8#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Low Iq Step-dn DC/DC Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet