CY2XP22
Document Number: 001-10229 Rev. *H Page 7 of 14
Parameter Measurements
Figure 2. 3.3 V Output Load AC Test Circuit
Figure 3. 2.5 V Output Load AC Test Circuit
Figure 4. Output DC Parameters
Figure 5. Output Rise and Fall Time
SCOPE
V
DD
V
SS
LVPECL
50
50
Z = 50
Z = 50
CLK#
CLK
2V
-1.3V +/- 0.165V
SCOPE
V
DD
V
SS
LVPECL
50
50
Z = 50
Z = 50
CLK#
CLK
2V
-0.5V +/- 0.125V
CLK
V
A
V
B
CLK#
V
OD
V
OCM
= (V
A
+ V
B
)/2
20%
80%
T
R
CLK
20%
80%
CLK#
T
F
CY2XP22
Document Number: 001-10229 Rev. *H Page 8 of 14
Figure 6. RMS Phase Jitter
Figure 7. Output Duty Cycle
Parameter Measurements (continued)
Phase noise
Phase noise mask
Offset Frequency
f1
f2
RMS Jitter =
Area Under the Masked Phase Noise Plot
Noise
Power
CLK
T
PW
T
PERIOD
T
DC
=
T
PW
T
PERIOD
CLK#
CY2XP22
Document Number: 001-10229 Rev. *H Page 9 of 14
Application Information
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter
performance, use good power supply isolation practices.
Figure 8 illustrates a typical filtering scheme. Since all the current
flows through pin 1, the resistance and inductance between this
pin and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A 1 to 10 µF ceramic or
tantalum capacitor is located in the general vicinity of this device
and may be shared with other devices.
Figure 8. Power Supply Filtering
Termination for LVPECL Output
The CY2XP22 implements its LVPECL driver with a current
steering design. For proper operation, it requires a 50 ohm dc
termination on each of the two output signals. For 3.3 V
operation, this data sheet specifies output levels for termination
to V
DD
– 2.0 V. This same termination voltage can also be used
for V
DD
= 2.5 V operation, or it can be terminated to V
DD
– 1.5 V.
Note that it is also possible to terminate with 50 ohms to ground
(V
SS
), but the high and low signal levels differ from the data sheet
values. Termination resistors are best located close to the
destination device. To avoid reflections, trace characteristic
impedance (Z
0
) should match the termination impedance.
Figure 9 shows a standard termination scheme.
Figure 9. LVPECL Output Termination
Crystal Interface
The CY2XP22 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in Figure 10 are
determined using a 25 MHz 18 pF parallel resonant crystal and
are chosen to minimize the ppm error. Note that the optimal
values for C1 and C2 depend on the parasitic trace capacitance
and are thus layout dependent.
Figure 10. Crystal Input Interface
3.3V
10µ
F
F
V
DD
V
DD
0.01 µF
(Pin 1)
(Pin 8)
CLK
84
84
Z0 = 50
Z0 = 50
3.3V
125 125
IN
CLK#
Device
XIN
XOUT
X1
18 pF Parallel
Crystal
C1
30 pF
C2
27 pF

CY2XP22ZXCT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC CLOCK GEN PLL LVPECL 8TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet