FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841604 DATA SHEET
2 REVISION A 4/17/15
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLDOWN
Input Pulldown Resistor 51 kΩ
TABLE 3D. REF_SEL FUNCTION TABLE
TABLE 3C. MR/nOE FUNCTION TABLE
TABLE 3B. BYPASS FUNCTION TABLE
Number Name Type Description
1 REF_SEL Input Pulldown
Reference select. Selects the input reference source.
LVCMOS/LVTTL interface levels. See Table 3D.
2 REF_IN Input Pulldown LVCMOS/LVTTL PLL reference clock input.
3, 8, 14,
24
V
DD
Power Core supply pins.
4, 13, 19 GND Power Power supply ground.
5, 6
XTAL_IN,
XTAL_OUT
Input
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
7 MR/nOE Input Pulldown
Active HIGH master reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the outputs are in high impedance (Hi-Z). When
logic LOW, the internal dividers and the outputs are enabled. Asynchronous
function. LVCMOS/LVTTL interface levels. See Table 3C.
9, 10, 11,
12
nc Unused No connect.
15, 16 Q0, nQ0 Output Differential output pair. HCSL interface levels.
17, 18 Q1, nQ1 Output Differential output pair. HCSL interface levels.
20, 21 Q2, nQ2 Output Differential output pair. HCSL interface levels.
22, 23 Q3, nQ3 Output Differential output pair. HCSL interface levels.
25 FSEL Input Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3A.
26 IREF Output
HCSL current reference resistor output. An external fi xed precision resistor
(475W) from this pin to ground provides a reference current used for differen-
tial current-mode Qx/nQx clock outputs.
27 BYPASS Input Pulldown
Selects PLL operation/PLL bypass operation. Asynchronous function. LLVC-
MOS/LVTTL interface levels. See Table 3B.
28 V
DDA
Power Analog supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3A. FSEL FUNCTION TABLE (f
ref
= 25MHZ)
Input Outputs
FSEL N Q0:1/nQ0:1
0 5 VCO/5 (100MHz) PCIe (default)
1 4 VCO/4 (125MHz) sRIO
Input
REF_SEL Input Reference
0 XTAL (default)
1 REF_IN
Input
MR/nOE Function
0 Outputs enabled (default)
1 Device reset, outputs disabled (high-impedance)
Input
BYPASS PLL Confi guration
0 PLL enabled (default)
1 PLL bypassed (f
OUT
= f
REF
÷ N)
