FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841604 DATA SHEET
4 REVISION A 4/17/15
TABLE 6. AC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency
VCO/5 100 MHz
VCO/4 125 MHz
tjit(Ø) RMS Phase Jitter (Random); NOTE 1
100MHz, (1.875MHz - 20MHz) 0.36 ps
125MHz, (1.875MHz - 20MHz) 0.45 ps
T
j
Phase Jitter Peak-to-Peak; NOTE 2
100MHz, (1.2MHz – 50MHz),
10
6
samples, 25MHz crystal input
12.81 ps
125MHz, (1.2MHz – 62.5MHz),
10
6
samples, 25MHz crystal input
12.30 ps
T
REFCLK_HF_RMS
Phase Jitter RMS; NOTE 3
100MHz, 10
6
samples,
25MHz crystal input
1.32 ps rms
125MHz, 10
6
samples,
25MHz crystal input
1.19 ps rms
tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 50 ps
tsk(o) Output Skew; NOTE 4, 5 75 ps
Rise Edge
Rate
Rising Edge Rate; NOTE 6, 7 0.6 4 V/ns
Fall Edge Rate Falling Edge Rate; NOTE 6, 7 0.6 4 V/ns
V
RB
Ringback Voltage; NOTE 6, 8 -100 100 mV
V
MAX
Absolute Max. Output Voltage; NOTE
9, 10
1150 mV
V
MIN
Absolute Min. Output Voltage; NOTE
9, 11
-300 mV
V
CROSS
Absolute Crossing Voltage;
NOTE 9, 12, 13
250 550 mV
DV
CROSS
Total Variation of V
Cross
over all edges;
NOTE 9, 12, 14
140 mV
odc Output Duty Cycle; NOTE 6, 15 48 52 %
T
STABLE
Power-up Stable Clock Output; NOTE
6, 8
500 ps
t
L
PLL Lock Time 90 ms
NOTE: All specifi cations are taken at 100MHz and 125MHz.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: RMS jitter after applying system transfer function. See IDT Application Note, PCI Express Reference Clock Requirements. Maximum
limit for PCI Express is 86ps peak-to-peak.
NOTE 3: RMS jitter after applying system transfer function. The pole frequencies for H1 and H2 for PCIe Gen 2 are 8-16MHz and 5-16MHz.
See IDT Application Note, PCI Express Reference Clock Requirements.Maximum limit for PCI Express Generation 2 is 3.1ps rms.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 5: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 6: Measurement taken from differential waveform.
NOTE 7: Measurement from -150mV to +150mV on the differential waveform (derived from Qx minus nQx).
The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the
differential zero crossing. See Parameter Measurement Information Section.
NOTE 8: T
STABLE
is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the V
RB
±100 differential range. See Parameter Measurement Information Section.
NOTE 9: Measurement taken from single ended waveform.
NOTE 10: Defi ned as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 11: Defi ned as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 12: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 13: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Refers to all crossing points for this measurement. See Parameter Measurement Information Section.
NOTE 14: Defi ned as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the V
CROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 15: Input duty cycle must be 50%.
