Microstepping Driver with Translator
A3967
15
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
For the latest version of this document, go to our website at:
www.allegromicro.com
Copyright ©2002-2013, Allegro MicroSystems, LLC
The products described here are manufactured under one or more U.S. patents, including U. S. Patent No. 5,684,427, or U.S. patents pending
Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
1.27
0.25
B
Reference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
B
0.20 ±0.10
0.41 ±0.10
2.20
0.65
9.60
1.27
21
24
A
15.40±0.20
2.65 MAX
10.30±0.33
7.50±0.10
C
SEATING
PLANE
C0.10
24X
For reference only
Pins 6 and 7, and 18 and 19 internally fused
Dimensions in millimeters
(Reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
E t d l d fi ti t li di ti ithi li it h
A
Terminal #1 mark area
GAUGE PLANE
SEATING PLANE
PCB Layout Reference View
4° ±4
0.27
+0.07
–0.06
0.84
+0.44
–0.43
21
24
Package LB 24-Pin SOIC
