Microstepping Driver with Translator
A3967
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS (continued) at T
A
= +25°C, V
BB
= 30 V, V
CC
= 3.0 V to 5.5V (unless
otherwise noted)
Characteristic Symbol Test Conditions
Limits
Min. Typ. Max. Units
Control Logic (cont’d)
Mixed Decay Trip Point PFDH 0.6V
CC
–V
PFDL 0.21V
CC
–V
Ref. Input Voltage Range V
REF
Operating 1.0 V
CC
V
Reference Input Impedance Z
REF
120 160 200 kΩ
Gain (G
m
) Error
(note 3)
E
G
V
REF
= 2 V, Phase Current = 38.37% † ±10 %
V
REF
= 2 V, Phase Current = 70.71% † ±5.0 %
V
REF
= 2 V, Phase Current = 100.00% † ±5.0 %
Thermal Shutdown Temp. T
J
165 °C
Thermal Shutdown Hysteresis T
J
–15°C
UVLO Enable Threshold V
UVLO
Increasing V
CC
2.45 2.7 2.95 V
UVLO Hysteresis V
UVLO
0.05 0.10 V
Logic Supply Current I
CC
Outputs enabled 50 65 mA
Outputs off 9.0 mA
Sleep mode 20 μA
* Operation at a step frequency greater than the speci ed minimum value is possible but not warranteed.
† 8 microstep/step operation.
NOTES: 1. Typical Data is for design information only.
2. Negative current is de ned as coming out of (sourcing) the speci ed device terminal.
3. E
G
= ([V
REF
/8] – V
SENSE
)/(V
REF
/8)
Microstepping Driver with Translator
A3967
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Device Operation. The A3967 is a complete microstep-
ping motor driver with built in translator for easy operation
with minimal control lines. It is designed to operate bipolar
stepper motors in full-, half-, quarter- and eighth-step
modes. The current in each of the two output full bridges
is regulated with xed off time pulse-width modulated
(PWM) control circuitry. The full-bridge current at each
step is set by the value of an external current sense resis-
tor (R
S
), a reference voltage (V
REF
), and the DACs output
voltage controlled by the output of the translator.
At power up, or reset, the translator sets the DACs and
phase current polarity to initial home state (see gures for
home-state conditions), and sets the current regulator for
both phases to mixed-decay mode. When a step command
signal occurs on the STEP input the translator automati-
cally sequences the DACs to the next level (see table 2 for
the current level sequence and current polarity). The mic-
rostep resolution is set by inputs MS
1
and MS
2
as shown in
table 1. If the new DAC output level is lower than the pre-
vious level the decay mode for that full bridge will be set
by the PFD input (fast, slow or mixed decay). If the new
DAC level is higher or equal to the previous level then the
decay mode for that Full bridge will be slow decay. This
automatic current-decay selection will improve microstep-
ping performance by reducing the distortion of the current
waveform due to the motor BEMF.
Reset Input (RESET). The RESET input (active low)
sets the translator to a prede ned home state (see gures
for home state conditions) and turns off all of the outputs.
STEP inputs are ignored until the RESET input goes high.
Step Input (STEP). A low-to-high transition on the
STEP input sequences the translator and advances the
motor one increment. The translator controls the input to
the DACs and the direction of current ow in each wind-
ing. The size of the increment is determined by the state of
inputs MS
1
and MS
2
(see table 1).
Microstep Select (MS
1
and MS
2
). Input terminals
MS1 and MS
2
select the microstepping format per
table 1. Changes to these inputs do not take effect until the
STEP command (see gure).
Direction Input (DIR). The state of the DIRECTION
input will determine the direction of rotation of the motor.
Internal PWM Current Control. Each full bridge is
controlled by a xed off-time PWM current-control cir-
cuit that limits the load current to a desired value (I
TRIP
).
Initially, a diagonal pair of source and sink outputs are
enabled and current ows through the motor winding and
R
S
. When the voltage across the current-sense resistor
equals the DAC output voltage, the current-sense compara-
tor resets the PWM latch, which turns off the source driver
(slow-decay mode) or the sink and source drivers (fast- or
mixed-decay modes).
The maximum value of current limiting is set by the
selection of R
S
and the voltage at the V
REF
input with a
transconductance function approximated by:
I
TRIP
max = V
REF
/8R
S
The DAC output reduces the V
REF
output to the cur-
rent-sense comparator in precise steps (see table 2 for %
I
TRIP
max at each step).
I
TRIP
= (% I
TRIP
max/100) x I
TRIP
max
Fixed Off-Time. The internal PWM current-control
circuitry uses a one shot to control the time the driver(s)
remain(s) off. The one shot off-time, t
off
, is determined by
the selection of an external resistor (R
T
) and capacitor (C
T
)
connected from the RC timing terminal to ground. The off
time, over a range of values of C
T
= 470 pF to 1500 pF and
R
T
= 12 kΩ to 100 kΩ is approximated by:
t
off
= R
T
C
T
Functional Description
Microstepping Driver with Translator
A3967
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
RC Blanking. In addition to the xed off-time of the
PWM control circuit, the C
T
component sets the compara-
tor blanking time. This function blanks the output of the
current-sense comparator when the outputs are switched by
the internal current-control circuitry. The comparator out-
put is blanked to prevent false overcurrent detection due
to reverse recovery currents of the clamp diodes, and/or
switching transients related to the capacitance of the load.
The blank time t
BLANK
can be approximated by:
t
BLANK
= 1400C
T
Enable Input (ENABLE). This active-low input enables
all of the outputs. When logic high the outputs are dis-
abled. Inputs to the translator (STEP, DIRECTION, MS
1
,
MS
2
) are all active independent of the ENABLE input
state.
Shutdown. In the event of a fault (excessive junction
temperature) the outputs of the device are disabled until
the fault condition is removed. At power up, and in the
event of low V
CC
, the under-voltage lockout (UVLO)
circuit disables the drivers and resets the translator to the
home state.
Sleep Mode (SLEEP). An active-low control input used
to minimize power consumption when not in use. This dis-
ables much of the internal circuitry including the outputs.
A logic high allows normal operation and startup of the
device in the home position.
Percent Fast Decay Input (PFD). When a STEP input
signal commands a lower output current from the previous
step, it switches the output current decay to either slow-,
fast-, or mixed-decay depending on the voltage level at the
PFD input. If the voltage at the PFD input is greater than
0.6V
CC
then slow-decay mode is selected. If the voltage on
the PFD input is less than 0.21V
CC
then fast-decay mode is
selected. Mixed decay is between these two levels.
Mixed Decay Operation. If the voltage on the PFD in-
put is between 0.6V
CC
and 0.21V
CC
, the bridge will oper-
ate in mixed-decay mode depending on the step sequence
(see gures). As the trip point is reached, the device will
go into fast-decay mode until the voltage on the RC termi-
nal decays to the voltage applied to the PFD terminal. The
time that the device operates in fast decay is approximated
by:
t
FD
= R
T
C
T
In (0.6V
CC
/V
PFD
)
After this fast decay portion, t
FD
, the device will
switch to slow-decay mode for the remainder of the xed
off-time period.
Functional Description (cont’d)
Typical output saturation voltages show-
ing Satlington sink-driver operation.
200
Dwg. GP-064-1A
007004
300
OUTPUT CURRENT IN MILLIAMPERES
2.0
OUTPUT SATURATION VOLTAGE IN VOLTS
1.0
0
0.5
1.5
2.5
500
600
T
A
= +25°C
SOURCE DRIVER
SINK DRIVER

A3967SLB

Mfr. #:
Manufacturer:
Description:
IC MTR DRV BIPOLAR 3-5.5V 24SOIC
Lifecycle:
New from this manufacturer.
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