74AUP1Z04 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 9 August 2012 18 of 28
NXP Semiconductors
74AUP1Z04
Low-power X-tal driver with enable and internal resistor
13.1.1 Design
Figure 14 shows the recommended way to connect a crystal to the 74AUP1Z04. This
circuit is basically a Pierce oscillator circuit in which the crystal is operating at its
fundamental frequency and is tuned by the parallel load capacitance of C
1
and C
2
. C
1
and
C
2
are in series with the crystal. They should be approximately equal. R
1
is the
drive-limiting resistor and is set to approximately the same value as the reactance of C
1
at
the crystal frequency (R
1
=X
C1
). This will result in an input to the crystal of 50 % of the
rail-to-rail output of X2. This keeps the drive level into the crystal within drive
specifications (the designer should verify this). Overdriving the crystal can cause damage.
The internal bias resistor provides negative feedback and sets a bias point of the inverter
near mid-supply, operating the 74AUP1GU04 portion in the high gain linear region.
To calculate the values of C
1
and C
2
, the designer can use the formula:
C
L
is the load capacitance as specified by the crystal manufacturer, C
s
is the stray
capacitance of the circuit (for the 74AUP1Z04 this is equal to an input capacitance
of 1.5 pF).
(1) resonance
(2) anti-resonance
(3) load resonance
Fig 13. Reactance and resistance characteristics of a crystal
001aai362
R
1
f
r
f
r
f
resistance
reactance
f
a
R
L
f
L
f
resistance
reactance
f
a
R
p
f
L
f
resistance
reactance
f
a
0
+
0
+
0
+
C
X1
C
X0
L
X1
R
X1
C
X1
C
L
C
L
C
X0
L
X1
R
X1
C
X1
C
X0
L
X1
R
X1
(3)
(2)
(1)
C
L
C
1
C
2
C
1
C
2
+
-------------------
C
s
+=
