102016© Integrated Device Technology, Inc. Revision E, January 5, 2016
8545 Datasheet
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 2. In a 100 differential
transmission line environment, LVDS drivers require a matched load
termination of 100 across near the receiver input. For a multiple
LVDS outputs buffer, if only partial outputs are used, it is
recommended to terminate the unused outputs.
Figure 2. Typical LVDS Driver Termination
3.3V
LVDS Driver
R1
100Ω
+
3.3V
50Ω
50Ω
100
Ω
Differential Transmission Line
112016© Integrated Device Technology, Inc. Revision E, January 5, 2016
8545 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 8545.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 8545 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 50mA = 173.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a moderate air
flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.173W * 66.6°C/W = 81.5°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (single layer or multi-layer).
Table 6. Thermal Resitance
JA
for 20 Lead TSSOP, Forced Convection
JA
by Velocity
Linear Feet per Minute 0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
122016© Integrated Device Technology, Inc. Revision E, January 5, 2016
8545 Datasheet
Reliability Information
Table 7.
JA
vs. Air Flow Table for a 20 Lead TSSOP
Transistor Count
The transistor count for 8545 is: 644
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions
Reference Document: JEDEC Publication 95, MO-153
JA
by Velocity
Linear Feet per Minute 0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
All Dimensions in Millimeters
Symbol Minimum Maximum
N 20
A 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 6.40 6.60
E 6.40 Basic
E1 4.30 4.50
e 0.65 Basic
L 0.45 0.75
aaa 0.10

8545BGLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 1-to-4 LVCMOS/LVTTL- to-LVDS Fanout Buffe
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet