MPR121
Sensors
20 Freescale Semiconductor, Inc.
These registers control GPIO and LED driver functions. D7~D0 bits correspond to GPIO and LED functions on ELE11~ ELE4
inputs respectively. When any of these ports are not used for electrode sensing, it can be used for GPIO or LED driver. The GPIO
control registers can be write at anytime regardless Stop Mode or Run mode. The configuration of the LED driver and GPIO
system is described with more detail in application note AN3894.
Note: The number of touch sensing electrodes, and therefore the number of GPIO ports left available is configured by the ECR
(0x5E) and GPIO Enable Register (0x77). ECR has higher priority and overrides the GPIO enabled in 0x77, that is when a pin is
enabled as GPIO but is also selected as electrode by ECR, the GPIO function is disabled immediately and it becomes an
electrode during Run Mode.
In the Stop Mode just after power-on reset, all electrodes and GPIO ports are in high impedance as all the GPIO ports are default
disabled and the electrodes are not enabled.
EN, DIR, CTL0, CTL1: GPIO enable and configuration bits, the functions are in description table below.
When the EN bit is set, the corresponding GPIO pin is enabled and the GPIO function is configured by CTL0, CTL1 and DIR bits.
When the port is used as an input, it can be configured as a normal logic input with high impedance (CTL0CTL1 = 2b00), input
with internal pull-down (CTL0CTL1 = 2b10) or pullup (CTL0CTL1 = 2b11). Note: the former may result in an unstable logic input
state if opened without fixed logic level input.
The GPIO output configuration can be configured as either push pull (CTL0CTL1 = 2b00) or open drain. When the GPIO is used
for LED drivers, the GPIO is set to high side only open drain (CTL0CTL1 = 2b11), which is can source up to 12 mA current into
the LED.
DAT: GPIO Data Register bits.
When a GPIO is enabled as an output, the GPIO port outputs the corresponding DAT bit level from GPIO Data Register (0x075).
The output level toggle remains on during any electrode charging. The level transition will occur after the ADC conversion takes
place. It is important to note that reading this register returns the content of the GPIO Data Register, (not a level of the port). When
a GPIO is configured as input, reading this register returns the latched input level of the corresponding port (not contents of the
GPIO Data Register). Writing to the DAT changes content of the register, but does not effect the input function.
SET: Writing a “1” to this bit will set the corresponding bit in the Data Register.
CLR: Writing a “1” to this bit will clear the corresponding bit in the Data Register.
TOG: Writing a “1” to this bit will toggle the corresponding bit in the Data Register
Writing “1” into the corresponding bits of GPIO Data Set Register, GPIO Data Clear Register, and GPIO Data Toggle Register will
set/clear/toggle contents of the corresponding DAT bit in Data Register. Writing “0” has no meaning. These registers allow any
individual port(s) to be set, cleared, or toggled individually without effecting other ports. It is important to note that reading these
registers returns the contents of the GPIO Data Register reading.
Direction Register(0x76) DIR_E11 DIR_E10 DIR_E9 DIR_E8 DIR_E7 DIR_E6 DIR_E5 DIR_E4
Enable Register(0x77) EN_E11 EN_E10 EN_E9 EN_E8 EN_E7 EN_E6 EN_E5 EN_E4
Data Set Register(0x78) SET_E11 SET_E10 SET_E9 SET_E8 SET_E7 SET_E6 SET_E5 SET_E4
Data Clear Register(0x79) CLR_E11 CLR_E10 CLR_E9 CLR_E8 CLR_E7 CLR_E6 CLR_E5 CLR_E4
Data Toggle Register(0x7A) TOG_E11 TOG_E10 TOG_E11 TOG_E8 TOG_E7 TOG_E6 TOG_E5 TOG_E4
EN DIR CTL0:CTL1 Function Description
0 X XX GPIO function is disabled. Port is high-z state.
1 0 00 GPIO port becomes input port.
1 0 10 GPIO port becomes input port with internal pulldown.
1 0 11 GPIO port becomes input port with internal pullup.
1 0 01 Not defined yet (as same as CTL = 00).
1 1 00 GPIO port becomes CMOS output port.
1 1 11 GPIO port becomes high side only open drain output port for LED driver.
1 1 10 GPIO port becomes low side only open drain output port.
1 1 01 Not defined yet (as same as CTL = 00).
GPIO Registers (0x73~0x7A)
